#include <stdlib.h>#include <string.h>#include <unistd.h>#include <stdio.h>#include <sys/time.h>#include "dbg_msg.h"#include "jt_arm.h"#include "jt_cortex.h"#include "jt_instr.h"#include "convert.h"DAP interface for ARM Cortex-M3
| #define DPACC_PORT_0 0 |
reserved
| #define DPACC_PORT_4 1 |
DP Ctrl/Stat register
Referenced by jtag_cotrex_DpCtrl_RegWrite(), and jtag_cotrex_DpStat_RegRead().
| #define DPACC_PORT_8 2 |
DP Select AP-Bank/AP-Sel
Referenced by jtag_cotrex_DpSelect_RegWrite().
| #define DPACC_PORT_12 3 |
DP RDBUFF (get final result)
Referenced by jtag_cotrex_DpRdBuff_RegRead().
| #define SEL_AHB_AP 0 |
provides access to system Advanced High performance Bus
Referenced by jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cortex_ApAHB_BankedDataRegWrite(), jtag_cortex_ApAHB_CtrlRegWrite(), jtag_cortex_ApAHB_DataRegRead(), jtag_cortex_ApAHB_DataRegWrite(), jtag_cortex_ApAHB_IdRegRead(), jtag_cortex_ApAHB_ROMbaseRegRead(), jtag_cortex_ApAHB_StatRegRead(), and jtag_cortex_ApAHB_TarRegWrite().
| #define SEL_APB_AP 1 |
provides access to debug Advanced Peripheral Bus
| #define SEL_JTAG_AP 2 |
provides JTAG access to on-chip components
| #define SEL_CORTEX_M3_AP 3 |
Cortex M3 auxiliary interface
| #define AHB_BANK_0 0 |
AP addr. range 0x00 , 0x04, 0x08, 0x0C
Referenced by jtag_cortex_ApAHB_CtrlRegWrite(), jtag_cortex_ApAHB_DataRegRead(), jtag_cortex_ApAHB_DataRegWrite(), jtag_cortex_ApAHB_StatRegRead(), and jtag_cortex_ApAHB_TarRegWrite().
| #define AHB_BANK_0_ADDR_CSW 0 |
AHB-AP Control/Status
Referenced by jtag_cortex_ApAHB_CtrlRegWrite(), and jtag_cortex_ApAHB_StatRegRead().
| #define AHB_BANK_0_ADDR_TAR 1 |
AHB-AP Transfer Address
Referenced by jtag_cortex_ApAHB_TarRegWrite().
| #define AHB_BANK_0_ADDR_DRW 3 |
AHB-AP Data Read Write
Referenced by jtag_cortex_ApAHB_DataRegRead(), and jtag_cortex_ApAHB_DataRegWrite().
| #define AHB_BANK_1 1 |
AP addr. range 0x10 , 0x14, 0x18, 0x1C
Referenced by jtag_cortex_ApAHB_BankedDataRegRead(), and jtag_cortex_ApAHB_BankedDataRegWrite().
| #define AHB_BANK_1_ADDR_BD0 0 |
AHB-AP Banked Data 0
Referenced by jtag_cortex_ApAHB_BankedDataRegRead(), and jtag_cortex_ApAHB_BankedDataRegWrite().
| #define AHB_BANK_1_ADDR_BD1 1 |
AHB-AP Banked Data 1
| #define AHB_BANK_1_ADDR_BD2 2 |
AHB-AP Banked Data 2
| #define AHB_BANK_1_ADDR_BD3 3 |
AHB-AP Banked Data 3
| #define AHB_BANK_15 15 |
AP addr. range 0xF0 , 0xF4, 0xF8, 0xFC
Referenced by jtag_cortex_ApAHB_IdRegRead(), and jtag_cortex_ApAHB_ROMbaseRegRead().
| #define AHB_BANK_15_ADDR_ROM 2 |
AHB-AP Debug ROM table
Referenced by jtag_cortex_ApAHB_ROMbaseRegRead().
| #define AHB_BANK_15_ADDR_IDR 3 |
AHB-AP Identification Register
Referenced by jtag_cortex_ApAHB_IdRegRead().
| static void jtag_cortex_dpacc_RegWrite | ( | uint32_t | data, | |
| char | port, | |||
| char * | AckFlag, | |||
| uint32_t * | retVal | |||
| ) | [static] |
Write - Debug Port Access Register
[bits 34..3] = Data[31..0]
[bits 2,1] = port A[3,2]
[bit 0] = 0 -> Write
| data | Write value | |
| port | address 4-> DP_Ctrl; 2-> DP_Select; 3-> DP_RDBUFF (get final result) | |
| AckFlag | pointer to save Ack: ether 1->Wait or 2->OK(or Fault) | |
| retVal | return value of previous DAP sequence |
References DBG_LEVEL_JTAG_ICERT_LOW, dbgPrintf(), DPACC, instr_dpacc, jtag_exchange_data(), jtag_send_instr(), jtag_supp_bitstr2int_MSB_First(), jtag_supp_int2bitstr_MSB_First(), transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cotrex_DpCtrl_RegWrite(), and jtag_cotrex_DpSelect_RegWrite().
| static uint32_t jtag_cortex_dpacc_RegRead | ( | char | port, | |
| char * | AckFlag | |||
| ) | [static] |
Read - Debug Port Access Register
[bits 34..3] = Data[31..0] forced to be 0
[bits 2,1] = port A[3,2]
[bit 0] = 1 -> Read
| port | address 4-> DP_Ctrl; 2-> DP_Select; 3-> DP_RDBUFF (get final result) | |
| AckFlag | pointer to save Ack: ether 1->Wait or 2->OK(or Fault) |
References DBG_LEVEL_JTAG_ICERT_LOW, dbgPrintf(), DPACC, instr_dpacc, jtag_exchange_data(), jtag_send_instr(), jtag_supp_bitstr2int_MSB_First(), jtag_supp_int2bitstr_MSB_First(), transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cotrex_DpRdBuff_RegRead(), and jtag_cotrex_DpStat_RegRead().
| static void jtag_cortex_apacc_RegWrite | ( | uint32_t | data, | |
| char | port, | |||
| char * | AckFlag, | |||
| uint32_t * | retVal | |||
| ) | [static] |
Write - Access Port Access Register
[bits 34..3] = Data[31..0]
[bits 2,1] = port A[3,2]
[bit 0] = 0 -> Write
| data | Write value | |
| port | address 4-> DP_Ctrl; 2-> DP_Select; 3-> DP_RDBUFF (get final result) | |
| AckFlag | pointer to save Ack: ether 1->Wait or 2->OK(or Fault) | |
| retVal | return value of previous DAP sequence |
References APACC, DBG_LEVEL_JTAG_ICERT_LOW, dbgPrintf(), instr_apacc, jtag_eos(), jtag_exchange_data(), jtag_send_instr(), jtag_supp_bitstr2int_MSB_First(), jtag_supp_int2bitstr_MSB_First(), NON, transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_ApAHB_BankedDataRegWrite(), jtag_cortex_ApAHB_CtrlRegWrite(), jtag_cortex_ApAHB_DataRegWrite(), and jtag_cortex_ApAHB_TarRegWrite().
| static uint32_t jtag_cortex_apacc_RegRead | ( | char | port, | |
| char * | AckFlag | |||
| ) | [static] |
Read - Access Port Access Register
[bits 34..3] = Data[31..0] forced to be 0
[bits 2,1] = port A[3,2]
[bit 0] = 1 -> Read
| port | address 4-> DP_Ctrl; 2-> DP_Select; 3-> DP_RDBUFF (get final result) | |
| AckFlag | pointer to save Ack: ether 1->Wait or 2->OK(or Fault) |
References APACC, DBG_LEVEL_JTAG_ICERT_LOW, dbgPrintf(), instr_apacc, jtag_eos(), jtag_exchange_data(), jtag_send_instr(), jtag_supp_bitstr2int_MSB_First(), jtag_supp_int2bitstr_MSB_First(), NON, transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cortex_ApAHB_DataRegRead(), jtag_cortex_ApAHB_IdRegRead(), jtag_cortex_ApAHB_ROMbaseRegRead(), and jtag_cortex_ApAHB_StatRegRead().
| uint32_t jtag_cotrex_DpStat_RegRead | ( | void | ) |
Send Read request to Debug Port Control / Status Register
[31] RO CSYSPWRUPACK System power-up acknowledge.
[30] R/W CSYSPWRUPREQ System power-up request.
After a reset this bit is LOW (0).
[29] RO CDBGPWRUPACK Debug power-up acknowledge.
[28] R/W CDBGPWRUPREQ Debug power-up request.
After a reset this bit is LOW (0).
[27] RO CDBGRSTACK Debug reset acknowledge.
[26] R/W CDBGRSTREQ Debug reset request.
After a reset this bit is LOW (0).
[25:24] - - Reserved, RAZ/SBZP
[21:12] R/W TRNCNT Transaction counter.
After a reset the value of this field is Unpredictable.
[11:8] R/W MASKLANE Indicates the bytes to be masked in pushed compare and pushed verify operations.
b1XXX Include byte lane 3 in comparisons. 0xFF------
bX1XX Include byte lane 2 in comparisons. 0x--FF----
bXX1X Include byte lane 1 in comparisons. 0x----FF--
bXXX1 Include byte lane 0 in comparisons. 0x------FF
If MASKLANE is set to b0000 or to b1111 then the comparison is made on the
complete word. In this case the mask is 0xFFFFFFFF.
After a reset the value of this field is Unpredictable.
[7:6] - - Reserved, RAZ/SBZP
[5] R/W STICKYERR This bit is set to 1 if an error is returned by an access port transaction.
To clear this bit: Write 1 to this bit of this register.
After a power-on reset this bit is LOW (0).
[4] R/W STICKYCMP This bit is set to 1 when a match occurs on a pushed compare or a pushed verify operation.
To clear this bit: Write 1 to this bit of this register.
After a power-on reset this bit is LOW (0).
[3:2] R/W TRNMODE This field sets the transfer mode for access port operations.
b00 Normal operation.
b01 Pushed verify operation.
b10 Pushed compare operation.
After a power-on reset the value of this field is Unpredictable.
[1] R/W STICKYORUN If overrun detection is enabled (see bit [0] of this register), this bit is set to
1 when an overrun occurs. To clear this bit: Write 1 to this bit of this register.
After a power-on reset this bit is LOW (0).
[0] R/W ORUNDETECT This bit is set to b1 to enable overrun detection.
After a reset this bit is LOW (0).
References DBG_LEVEL_GDB_ARM_INFO, dbgPrintf(), DPACC_PORT_4, jtag_cortex_dpacc_RegRead(), transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_AHB_attach(), and jtag_test().
| void jtag_cotrex_DpCtrl_RegWrite | ( | uint32_t | data | ) |
Write to Debug Port Control / Status Register
| data | Write value |
References DPACC_PORT_4, jtag_cortex_dpacc_RegWrite(), transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_AHB_attach().
| uint32_t jtag_cotrex_DpRdBuff_RegRead | ( | void | ) |
collect final data from Read Buffer
References DPACC_PORT_12, jtag_cortex_dpacc_RegRead(), transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_AHB_attach(), jtag_cortex_AHB_ReadByte(), jtag_cortex_AHB_ReadHalfword(), jtag_cortex_AHB_ReadWord(), jtag_cortex_AHB_ReadWordMemory(), jtag_cortex_core_ApplicationInterruptResetControl_ReadRegister(), jtag_cortex_core_BusFaultAddress_ReadRegister(), jtag_cortex_core_ConfigurationControl_ReadRegister(), jtag_cortex_core_CPUID_ReadRegister(), jtag_cortex_core_debugExceptionMonitorControl_ReadRegister(), jtag_cortex_core_DebugFaultStatus_ReadRegister(), jtag_cortex_core_debugHaltingControlStatus_ReadRegister(), jtag_cortex_core_HardFaultStatus_ReadRegister(), jtag_cortex_core_MemManageAddress_ReadRegister(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_ReadDebugReg(), jtag_cortex_core_restart(), jtag_cortex_core_StopRunningProgram(), jtag_cortex_core_WriteCpuRegs(), jtag_cortex_dwt_comp_RegRead(), jtag_cortex_dwt_ctrl_RegRead(), jtag_cortex_dwt_function_RegRead(), jtag_cortex_dwt_mask_RegRead(), jtag_cortex_fpb_comp_RegRead(), jtag_cortex_fpb_ctrl_RegRead(), and jtag_test().
| uint32_t jtag_cotrex_DpSelect_RegWrite | ( | char | AP_Sel, | |
| char | AP_Bank, | |||
| uint32_t * | value | |||
| ) |
DP Select (current access port and four word register window on current access port)
| AP_Sel | select AP (e.g. 0 for AHB-AP) | |
| AP_Bank | select bank to use (e.g. 0,1 or 15) | |
| value | pointer to store return value of previous DAP sequence |
| 0 | if not changed (nither Sel,Bank nor value) | |
| 1 | values changed |
References current_AP_Bank, current_AP_Sel, DPACC_PORT_8, jtag_cortex_dpacc_RegWrite(), transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cortex_ApAHB_BankedDataRegWrite(), jtag_cortex_ApAHB_CtrlRegWrite(), jtag_cortex_ApAHB_DataRegRead(), jtag_cortex_ApAHB_DataRegWrite(), jtag_cortex_ApAHB_IdRegRead(), jtag_cortex_ApAHB_ROMbaseRegRead(), jtag_cortex_ApAHB_StatRegRead(), and jtag_cortex_ApAHB_TarRegWrite().
| void jtag_cotrex_DpSelect_Invalidate | ( | void | ) |
Invalidate current bank and access port
References current_AP_Bank, and current_AP_Sel.
Referenced by jtag_cortex_core_restart().
| uint32_t jtag_cortex_ApAHB_StatRegRead | ( | void | ) |
Read AHB-AP Control/Status Register
[31:30] - Reserved. Read as 0b00.
[29] MasterType 0 = core.
1 = debug.
This bit cannot be cleared if COREACCEN = 0. Read back to confirm if accepted.
It cannot be changed if transaction is outstanding.
Debugger must first check TransinProg.
Reset value = 0b1.
[28:26] - Reserved, 0b000 (= Hprot432).
[25] Hprot1 User (0b0) / Privilege (0b1) control
Reset value = 0b1.
[24] - Reserved, 0b1 (= Hprot0).
[23:12] - Reserved, 0x000.
[11:8] Mode Mode of operation bits:
0x0 = normal download/upload mode
Reset value = 0x0.
[7] TransINProg Transfer in progress. This field indicates if a transfer is in progress on the APB master port.
[6] DbgStatus Indicates the status of the DBGEN port. If DbgStatus is LOW, no AHB transfers carried out.
1 = AHB transfers permitted.
0 = AHB transfers not permitted.
[5:4] AddrInc Auto address increment and pack mode on Read or Write data access.
Only increments if the current transaction completes with no error.
Auto address incrementing and packed transfers are not performed on access to Banked Data
registers 0x10 - 0x1C. The status of these bits is ignored in these cases.
Increments and wraps within a 4-KB address boundary, for example for word incrementing
from 0x1000 to 0x1FFC. If the start is at 0x14A0, then the counter increments to 0x1FFC, wraps to
0x1000, then continues incrementing to 0x149C.
0b00 = auto increment off.
0b01 = increment single. Single transfer from corresponding byte lane.
0b10 = increment packed.
0b11 = reserved. No transfer.
Size of address increment is defined by the Size field [2:0].
Reset value: 0b00.
[3] - Reserved 0b0.
[2:0] SIZE Size of access field:
0b000 = 8 bits
0b001 = 16 bits
0b010 = 32 bits
Reset value: b000.
References AHB_BANK_0, AHB_BANK_0_ADDR_CSW, error_exit_code, jtag_cortex_apacc_RegRead(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_AHB_attach(), and jtag_test().
| uint32_t jtag_cortex_ApAHB_CtrlRegWrite | ( | uint32_t | data | ) |
Write AHB-AP Control/Status Register
| data | Write value |
References AHB_BANK_0, AHB_BANK_0_ADDR_CSW, jtag_cortex_apacc_RegWrite(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_AHB_attach(), and jtag_cortex_AHB_setmodeTar().
| void jtag_cortex_ApAHB_TarRegWrite | ( | uint32_t | address | ) |
Write AHB-AP Transfer Address
| address | AHB-AP Transfer Address |
References AHB_BANK_0, AHB_BANK_0_ADDR_TAR, error_exit_code, jtag_cortex_apacc_RegWrite(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transactionPenting(), transaction::uplevel, and transaction::uplevelRefCnt.
Referenced by jtag_cortex_AHB_setmodeTar().
| uint32_t jtag_cortex_ApAHB_DataRegRead | ( | void | ) |
AHB-AP Data Read
References AHB_BANK_0, AHB_BANK_0_ADDR_DRW, jtag_cortex_apacc_RegRead(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_AHB_ReadByte(), jtag_cortex_AHB_ReadHalfword(), jtag_cortex_AHB_ReadWord(), jtag_cortex_AHB_ReadWordMemory(), jtag_cortex_core_ApplicationInterruptResetControl_ReadRegister(), jtag_cortex_core_BusFaultAddress_ReadRegister(), jtag_cortex_core_ConfigurationControl_ReadRegister(), jtag_cortex_core_CPUID_ReadRegister(), jtag_cortex_core_DebugFaultStatus_ReadRegister(), jtag_cortex_core_HardFaultStatus_ReadRegister(), jtag_cortex_core_MemManageAddress_ReadRegister(), jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_restart(), jtag_cortex_dwt_ctrl_RegRead(), jtag_cortex_fpb_comp_RegRead(), and jtag_cortex_fpb_ctrl_RegRead().
| void jtag_cortex_ApAHB_DataRegWrite | ( | uint32_t | data | ) |
AHB-AP Data Write
| data | Write value |
References AHB_BANK_0, AHB_BANK_0_ADDR_DRW, jtag_cortex_apacc_RegWrite(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_AHB_WriteByte(), jtag_cortex_AHB_WriteHalfword(), jtag_cortex_AHB_WriteMemoryBuf(), jtag_cortex_AHB_WriteWord(), jtag_cortex_core_ApplicationInterruptResetControl_WriteRegister(), jtag_cortex_core_BusFaultAddress_WriteRegister(), jtag_cortex_core_ConfigurationControl_WriteRegister(), jtag_cortex_core_DebugFaultStatus_WriteRegister(), jtag_cortex_core_HardFaultStatus_WriteRegister(), jtag_cortex_core_MemManageAddress_WriteRegister(), jtag_cortex_core_restart(), jtag_cortex_dwt_ctrl_RegWrite(), jtag_cortex_fpb_comp_RegWrite(), and jtag_cortex_fpb_ctrl_RegWrite().
| uint32_t jtag_cortex_ApAHB_BankedDataRegRead | ( | char | idx | ) |
AHB-AP Banked Data [0..3] Read
| idx | window index 0,1,2 or 3 |
References AHB_BANK_1, AHB_BANK_1_ADDR_BD0, jtag_cortex_apacc_RegRead(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_core_debugExceptionMonitorControl_ReadRegister(), jtag_cortex_core_debugHaltingControlStatus_ReadRegister(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_ReadDebugReg(), jtag_cortex_core_StopRunningProgram(), jtag_cortex_core_WriteCpuRegs(), jtag_cortex_dwt_comp_RegRead(), jtag_cortex_dwt_function_RegRead(), jtag_cortex_dwt_mask_RegRead(), and jtag_test().
| void jtag_cortex_ApAHB_BankedDataRegWrite | ( | char | idx, | |
| uint32_t | data, | |||
| uint32_t * | ret_val | |||
| ) |
AHB-AP Banked Data [0..3] Write data value
| idx | window index 0,1,2 or 3 | |
| data | Write value | |
| ret_val | return value of previous DAP sequence |
References AHB_BANK_1, AHB_BANK_1_ADDR_BD0, jtag_cortex_apacc_RegWrite(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionActivate(), transactionCreate(), transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_core_debugExceptionMonitorControl_WriteRegister(), jtag_cortex_core_debugHaltingControlStatus_WriteRegister(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_ReadDebugReg(), jtag_cortex_core_StopRunningProgram(), jtag_cortex_core_WriteCpuRegs(), jtag_cortex_dwt_comp_RegWrite(), jtag_cortex_dwt_function_RegWrite(), jtag_cortex_dwt_mask_RegWrite(), and jtag_test().
| uint32_t jtag_cortex_ApAHB_ROMbaseRegRead | ( | void | ) |
AHB-AP Read Debug ROM base address
References AHB_BANK_15, AHB_BANK_15_ADDR_ROM, error_exit_code, jtag_cortex_apacc_RegRead(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_test().
| uint32_t jtag_cortex_ApAHB_IdRegRead | ( | void | ) |
AHB-AP Read Debug AHB-ID Register
References AHB_BANK_15, AHB_BANK_15_ADDR_IDR, error_exit_code, jtag_cortex_apacc_RegRead(), jtag_cotrex_DpSelect_RegWrite(), SEL_AHB_AP, transactionGet(), transactionPenting(), and transaction::uplevel.
Referenced by jtag_cortex_AHB_attach().
char current_AP_Bank = -1 [static] |
Referenced by jtag_cotrex_DpSelect_Invalidate(), and jtag_cotrex_DpSelect_RegWrite().
char current_AP_Sel = -1 [static] |
Referenced by jtag_cotrex_DpSelect_Invalidate(), and jtag_cotrex_DpSelect_RegWrite().