jt_cortex_core.c File Reference

#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/time.h>
#include "dbg_msg.h"
#include "jt_arm.h"
#include "jt_cortex.h"
#include "jt_instr.h"
#include "jt_tap.h"
#include <bitstring.h>
#include "arm_memory_mmap.h"
#include "arm_memory_workspace.h"
#include "convert.h"
#include "arm_gdbstub.h"

Functions

Detailed Description

Core Debug interface for ARM Cortex-M3

Function Documentation

static void jtag_cortex_core_GetBuff ( uint32_t  address,
uint32_t  startPos,
uint32_t  lastPos,
uint8_t *  buff 
) [static]

References jtag_cortex_AHB_ReadByte(), jtag_cortex_AHB_ReadWord(), and transaction::size.

Referenced by jtag_cortex_core_PollDbgState().

static void jtag_cortex_core_Buff2Queue ( uint8_t *  buff,
uint32_t  size 
) [static]

References ICESTATE_DCC_BUFFER_INQUEUE, and ICESTATE_DCC_BUFFER_IS_FULL.

Referenced by jtag_cortex_core_PollDbgState().

uint32_t jtag_cortex_core_debugHaltingControlStatus_ReadRegister ( void   ) 

Read Debug Halting Control and Status Register (DHCSR) twice
first access storen in CPU.ext.v7m.dhcsr
second held within return value.

 DHCSR-Status:
 [31-26]	res.
 [25]		S_RESET_ST
 [24]		S_RETIRE_ST
 [23-20]	res.
 [19]		S_LOCKUP
 [18]		S_SLEEP
 [17]		S_HALT
 [16]		S_REGRDY
 DHCSR-Control:
 [15-6]	res.
 [5]		C_SNAPSTALL
 [4]		res.
 [3]		C_MASKINTS
 [2]		C_STEP
 [1]		C_HALT
 [0]		C_DEBUGEN
Returns:
DHCSR value of last access

References AUTO_INCR_OFF_AP_CONTROL, CORE_DEBUG_BASE_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_core_restart(), and jtag_test().

void jtag_cortex_core_debugHaltingControlStatus_WriteRegister ( uint32_t  data  ) 

Write Debug Halting Control and Status Register (DHCSR)

Parameters:
data value to write to DHCSR
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, CORE_DEBUG_BASE_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegWrite(), and SIZE_WORD_AHB_AP_CONTROL.

Referenced by jtag_cortex_core_FinalExitDebug(), jtag_cortex_core_restart(), jtag_cortex_core_RunProgram(), jtag_cortex_core_Step(), and jtag_test().

uint32_t jtag_cortex_core_debugExceptionMonitorControl_ReadRegister ( void   ) 

Read Debug Exception and Monitor Control Register (DEMCR)
also storen in ice_state.cortex.demcr 

 [31-25]	res.	
 [24]		TRCENA
 [23-20]	res.	
 [19]		MON_REQ
 [18]		MON_STEP
 [17]		MON_PENG
 [16]		MON_EN
 [15-11]	res.	
 [10]		VC_HARDERR
 [9]		VC_INTERR
 [8]		VC_BUSERR
 [7]		VC_STATERR
 [6]		VC_CHKERR
 [5]		VC_NOCPERR
 [4]		VC_MMERR
 [3-1]	res.	
 [0]		VC_CORERESET
Returns:
DEMCR value

References AUTO_INCR_OFF_AP_CONTROL, CORE_DEBUG_BASE_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_core_restart(), and jtag_test().

void jtag_cortex_core_debugExceptionMonitorControl_WriteRegister ( uint32_t  data  ) 

Write Debug Exception and Monitor Control Register (DEMCR)

Parameters:
data value to write to DEMCR
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, CORE_DEBUG_BASE_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegWrite(), and SIZE_WORD_AHB_AP_CONTROL.

Referenced by jtag_cortex_core_restart(), and jtag_test().

uint32_t jtag_cortex_core_ApplicationInterruptResetControl_ReadRegister ( void   ) 

Read Application Interrupt/Reset Control Register (AIRCR)
also storen in ice_state.cortex.aircr
also updates arm_info.bigend 

 [15]		ENDIANESS	1=big; 0=little
 [14:11]			res.
 [10:8]	PRIGROUP	
 [2]		SYSRESETREQ	reset outer system (without debug)
 [1]		VECTCLRACTIVE	clear all state information for active NMI, fault, and interrupt
 [0]		VECTRESET	reset system (without debug)
Returns:
AIRCR value

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_ERROR, dbgPrintf(), jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), NVIC_AIRCR_ADDR, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by gdb_check_endian_at_reset_vector(), jtag_cortex_core_restart(), and jtag_test().

void jtag_cortex_core_ApplicationInterruptResetControl_WriteRegister ( uint32_t  data  ) 

Write Application Interrupt/Reset Control Register (AIRCR)

Parameters:
data value to write to AIRCR
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_ERROR, dbgPrintf(), jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), NVIC_AIRCR_ADDR, and SIZE_WORD_AHB_AP_CONTROL.

Referenced by jtag_cortex_core_restart(), and jtag_test().

uint32_t jtag_cortex_core_CPUID_ReadRegister ( void   ) 

Read CPU ID Register 

 [31:24]	IMPLEMENTER	Implementer code. ARM is 0x41
 [23:20]	VARIANT		Implementation defined variant number.
 [19:16]			Constant Reads as 0xF
 [15:4]	PARTNO		Number of processor within family:
  [15:14]			b11=Cortex family
  [13:12]			b00=version
  [11:10]			b00=reserved
  [9:8]			b10=M (v7-M)
  [7:4]			X=family member. Cortex-M3 is b0011.
 [3-0]	REVISION	revision number
Returns:
CCR value

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), NVIC_CPUID_ADDR, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_core_restart().

uint32_t jtag_cortex_core_ConfigurationControl_ReadRegister ( void   ) 

Read Configuration Control Register (CCR)
also storen in ice_state.cortex.ccr 

 [9]		STKALIGN	on exception entry do 8 byte SP alignment
 [8]		BFHFNMIGN	Bus Fault, Hard Fault, NMI ignore (don't use it)
 [7-5]			res.
 [4]		DIV_0_TRP	trap on divide by 0
 [3]		UNALIGN_TRP	trap for unaligned access
 [2]				res.
 [1]		USERSETMPEND	enables user code to write the Software Trigger Interrupt register
 [0]		NONEBASETHRDENA	Thread mode can be entered from any level in Handler mode by controlled return value.
Returns:
CCR value

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), NVIC_CCR_ADDR, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_core_restart(), and jtag_test().

void jtag_cortex_core_ConfigurationControl_WriteRegister ( uint32_t  data  ) 

Write Configuration Control Register (CCR)

Parameters:
data value to write to CCR
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), NVIC_CCR_ADDR, and SIZE_WORD_AHB_AP_CONTROL.

uint32_t jtag_cortex_core_HardFaultStatus_ReadRegister ( void   ) 

Read Hard Fault Status Register (HFSR)
also storen in ice_state.cortex.hfsr 

 [31]		DEBUGEVT
 [30]		FORCED
 [1]		VECTTBL
Returns:
HFSR value

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), NVIC_HFSR_ADDR, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_restart(), and jtag_test().

void jtag_cortex_core_HardFaultStatus_WriteRegister ( uint32_t  data  ) 

Write Hard Fault Status Register (HFSR)

Parameters:
data value to write to HFSR
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), NVIC_HFSR_ADDR, and SIZE_WORD_AHB_AP_CONTROL.

Referenced by jtag_cortex_core_restart().

uint32_t jtag_cortex_core_DebugFaultStatus_ReadRegister ( void   ) 

Read Debug Fault Status Register (DFSR)
also storen in ice_state.cortex.dfsr 

 [4]		EXTERNAL	External debug request flag
 [3]		VCATCH		Vector catch flag
 [2]		DWTTRAP		Data Watchpoint and Trace (DWT) flag
 [1]		BKPT		BKPT flag
 [0]		HALTED		Halt request flag
Returns:
DFSR value

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), NVIC_DFSR_ADDR, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_core_PollDbgState(), and jtag_cortex_core_restart().

void jtag_cortex_core_DebugFaultStatus_WriteRegister ( uint32_t  data  ) 

Write Debug Fault Status Register (DFSR)

Parameters:
data value to write to DFSR
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), NVIC_DFSR_ADDR, and SIZE_WORD_AHB_AP_CONTROL.

uint32_t jtag_cortex_core_MemManageAddress_ReadRegister ( void   ) 

Read Mem Manage Address Register (MMAR)
also storen in ice_state.cortex.mmar

Returns:
MMAR value

References AUTO_INCR_OFF_AP_CONTROL, CPU, reg_set::ext, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), reg_set::RegExt::RegV7mExt::mmar, NVIC_MMAR_ADDR, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, and reg_set::RegExt::v7m.

Referenced by jtag_cortex_core_ReadCpuRegs().

void jtag_cortex_core_MemManageAddress_WriteRegister ( uint32_t  data  ) 

Write Mem Manage Address Register (MMAR)

Parameters:
data value to write to MMAR
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), NVIC_MMAR_ADDR, and SIZE_WORD_AHB_AP_CONTROL.

uint32_t jtag_cortex_core_BusFaultAddress_ReadRegister ( void   ) 

Read Bus Fault Address Register (BFAR)
also storen in ice_state.cortex.bfar

Returns:
BFAR value

References AUTO_INCR_OFF_AP_CONTROL, reg_set::RegExt::RegV7mExt::bfar, CPU, reg_set::ext, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), NVIC_BFAR_ADDR, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, and reg_set::RegExt::v7m.

Referenced by jtag_cortex_core_ReadCpuRegs().

void jtag_cortex_core_BusFaultAddress_WriteRegister ( uint32_t  data  ) 

Write Bus Fault Address Register (BFAR)

Parameters:
data value to write to BFAR
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), NVIC_BFAR_ADDR, and SIZE_WORD_AHB_AP_CONTROL.

static uint32_t getTargetTempWordAddress ( void   )  [static]

References memMap::baseAddr, getWorkSpace(), memMap::memBufferType, MMAP_T_RAM, memMap::MemBufferType::Workspace::offset, memMap::MemBufferType::Workspace::state, memMap::type, memMap::MemBufferType::Workspace, WORKSPACE_BROKEN, and WORKSPACE_UNTESTED.

Referenced by jtag_cortex_core_WriteCpuRegs().

void jtag_cortex_core_ReadCpuRegs ( void   ) 

Read out ARM CPU core registers R0..R15 and xPSR, Main SP, Process SP.
Additional Regisers ICSR, VTOR SHCSR and CFSR are read.
The values are stored inside of the global structure named CPU.

 XPSR - Program Status Register


    

  • application PSR
 	[31]			N		flag negative
 	[30]			Z		flag zero
 	[29]			C		flag carry
 	[28]			V		flag overflow
 	[27]			Q		flag saturation
    • 

  • execution PSR (a: ICI - Interruptible Continuable Instruction)
 	[26,25]					res. = 0
 	[15-12]			REG_NUM		start pos in register list of LDM/STM
 	[11,10]					res. = 0
    • 

  • execution PSR (b: IT - state of If Then instruction)
 	[15,14,13]		IT_cond_base	condition pass if
 						0b000 Z set
 						0b001 C set
 						0b010 N set
 						0b011 V set
 						0b100 C set and Z clear
 						0b101 N == V
 						0b110 N == V and Z clear
 						0b111 always true
 	[12,11,10,26,25]	IT_size		P=0 exec. P=1 don't exec
 						0b00000	normal exec. not in IT block
 						0bP1000 entry point for 1 instr.
 						0bpP100 entry point for 2 instr.
 						0bPpP10 entry point for 3 instr.
 						0bpPpP1 entry point for 4 instr.
    • 

  • execution PSR
 	[24]			T		Thumb instruction (=1)
    • 

  • interrupt PSR
 	[8-0]			ISR_NUMBER	Number of preempted exception.
 
 
     ICSR - Interrupt Control State Register
 	[31]			NMIPENDSET	set pending NM
 	[30:29]					res.
 	[28]			PENDSVSET	set pending pendSV
 	[27]			PENDSVCLR	clear pending pendSV
 	[26]			PENDSTSET	set pending SysTick
 	[25]			PENDSTCLR	clear pending SysTick
 	[24]					res.
 	[23]			ISRPREEMPT	(to be used at debug time)
 						It indicates that a pending interrupt becomes active in the next running cycle. 
 						If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.
 	[22]			ISRPENDING	interrupt pending flag (excludes NMI and Faults)
 	[21:12]			VECTPENDIN	pending ISR number field
 	[11]			RETTOBASE	bit to indicate that an interrupt return will switch from handler to thread mode
 	[10,9]					res.
 	[8:0]			VECTACTIVE	active ISR number field
 
     
     VTOR - Vector Table Offest Register
	[31:30]					res.
	[29]			TBLBASE		Vector table base is in Code (0) or SRAM (1)
	[28:7]			TBLOFF		Vector table base offset field.
	[6:0]					res.
 
     
     SHCSR - System Handler Control and Status Register
	[31:19]					reserved
	[18]			USGFAULTENA	UsageFault enable
	[17]			BUSFAULTENA	BusFault enable
	[16]			MEMFAULTENA	MemManage enable
	[15]			SVCALLPENDED	SVCall is pending
	[14]			BUSFAULTPENDED	BusFault is pending
	[13]			MEMFAULTPENDED	MemManage is pending
	[12]			USGFAULTPENDED	UsageFault is pending
	[11]			SYSTICKACT	SysTick is active
	[10]			PENDSVACT	PendSV is active
	[9]					reserved
	[8]			MONITORACT	Monitor is active
	[7]			SVCALLACT	SVCall is active
	[6:4]					reserved
	[3]			USGFAULTACT	UsageFault is active
	[2]					reserved
	[1]			BUSFAULTACT	BusFault is active
	[0]			MEMFAULTACT	MemManage is active
 
     
     CFSR - Configurable Fault Status Register
    • 

  • Usage Fault Status Register
	[25]			DIVBYZERO  
	[24]			UNALIGNED
	[23:20]					reserved.
	[19]			NOCP		no coprocessor instructions
	[18]			INVPC		invalid PC instruction
	[17]			INVSTATE	invalid combination of EPSR and instruction
	[16]			UNDEFINSTR	undefined instruction
    • 

  • Bus Fault Status Register
	[15]			BFARVALID	Bus Fault Address Register (BFAR) contains a valid address
	[14:13]					reserved
	[12]			STKERR		Stacking from exception has caused one or more bus faults
	[11]			UNSTKERR	Unstack from exception return has caused one or more bus faults
	[10]			IMPRECISERR	Imprecise data bus error
	[9]			PRECISERR	Precise data bus error return
	[8]			IBUSERR		Instruction bus error flag:
    • 

  • Memory Manage Fault Status Register
	[7]			MMARVALID	Memory Manage Address Register (MMAR) address valid flag
	[6,5]					reserved
	[4]			MSTKERR		Stacking from exception has caused one or more access violations
	[3]			MUNSTKERR	Unstack from exception return has caused one or more access violations
	[2]					reserved
	[1]			DACCVIOL	Data access violation flag
	[0]			IACCVIOL	Instruction access violation flag
 
     
     packed control, faultmask, basepri, primask register
    • 

  • control
 	[31:26]					reserved
 	[25]			STACK		0= Main SP; 1= Process SP
 	[24]			ACCESS		0= Thread privileged access; 1= unprivileg access
    • 

  • faultmask
 	[23:17]					reserved
 	[16]			FM		0= exception enabled; 1= forward to hard fault
    • 

  • basepri
 	[15:12]					reserved
 	[11:8]			BASEPRI
    • 

  • primask
 	[7:1]					reserved
 	[0]			PM		0= interrupt enabled; 1= interrupt disabled
 
    • 



 
Parameters:

  

    
- 

  

  




Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, reg_set::RegExt::RegV7mExt::bfar, reg_set::RegExt::RegV7mExt::cfsr, reg_set::RegExt::RegV7mExt::control, CORE_DEBUG_BASE_ADDR, reg_set::CPSR, CPU, CPU_CPSR_FLAG_FAKE_CORTEX_M3, CPU_CPSR_FLAG_FIQ_DISABEL, CPU_CPSR_FLAG_IRQ_DISABEL, CPU_CPSR_FLAG_THUMB, CPU_CPSR_MODE_ABORT, CPU_CPSR_MODE_FIQ, CPU_CPSR_MODE_IRQ, CPU_CPSR_MODE_IRQ_26, CPU_CPSR_MODE_SVC, CPU_CPSR_MODE_SVC_26, CPU_CPSR_MODE_SYSTEM, CPU_CPSR_MODE_USER, DBG_LEVEL_GDB_ARM_INFO, dbgPrintf(), DHCSR_S_REGRDY, reg_set::ext, reg_set::RegExt::RegV7mExt::icsr, jtag_cortex_AHB_ReadWordMemory(), jtag_cortex_AHB_setmodeTar(), jtag_cortex_AHB_WriteMemoryBuf(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cortex_ApAHB_BankedDataRegWrite(), jtag_cortex_ApAHB_DataRegRead(), jtag_cortex_core_BusFaultAddress_ReadRegister(), jtag_cortex_core_HardFaultStatus_ReadRegister(), jtag_cortex_core_MemManageAddress_ReadRegister(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_Step(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), reg_set::RegExt::RegV7mExt::mmar, NVIC_CFSR_ADDR, NVIC_ICSR_ADDR, NVIC_SHCSR_ADDR, NVIC_VTOR_ADDR, transaction::parameter, reg_set::RegExt::RegV7mExt::prev_xPSR, reg_set::Regs::r, reg_set::regs, reg_set::RegExt::RegV7mExt::shcsr, SIZE_WORD_AHB_AP_CONTROL, reg_set::RegExt::RegV7mExt::sp_main, reg_set::RegExt::RegV7mExt::sp_process, SYSM_BASEPRI, SYSM_CONTROL, SYSM_FAULTMASK, SYSM_PRIMASK, THUMB2_MRS_P1, THUMB2_MRS_P2, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, reg_set::RegExt::v7m, reg_set::RegExt::RegV7mExt::vtor, and reg_set::RegExt::RegV7mExt::xPSR.

Referenced by jtag_arm_ReadCpuRegs(), jtag_cortex_core_restart(), and jtag_test().

void jtag_cortex_core_WriteCpuRegs ( int  writeXPSR,
int  writeStackPointer 
)

Write back the stored CPU register (R0 .. R15) to the ARM core.
If writeXPSR is not zero write back xPSR, too.
If writeStackPointer is not zero write back Main_SP and Process_SP, too
But without the additional Regisers like ICSR, VTOR SHCSR and CFSR.
(This function is used for test only.)

Parameters:
writeXPSR (!= 0) if xPSR has to be changed
writeStackPointer (!= 0) if StackPointers has to be changed
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, CORE_DEBUG_BASE_ADDR, CPU, DBG_LEVEL_GDB_ARM_INFO, dbgPrintf(), DHCSR_C_DEBUGEN, DHCSR_S_HALT, DHCSR_S_REGRDY, error_exit_code, reg_set::ext, getTargetTempWordAddress(), jtag_cortex_AHB_ReadWord(), jtag_cortex_AHB_setmodeTar(), jtag_cortex_AHB_WriteWord(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cortex_ApAHB_BankedDataRegWrite(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_Step(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), transaction::parameter, reg_set::RegExt::RegV7mExt::prev_xPSR, reg_set::Regs::r, reg_set::regs, SIZE_WORD_AHB_AP_CONTROL, reg_set::RegExt::RegV7mExt::sp_main, reg_set::RegExt::RegV7mExt::sp_process, SYSM_APSR, THUMB2_MSR_P1, THUMB2_MSR_P2, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, reg_set::RegExt::v7m, and reg_set::RegExt::RegV7mExt::xPSR.

Referenced by jtag_arm_WriteCpuRegs(), jtag_cortex_core_PrepareExitDebug(), jtag_cortex_core_RunProgram(), and jtag_cortex_core_Step().

uint32_t jtag_cortex_core_ReadDebugReg ( int  regnum  ) 

Read Debug Core Register

Parameters:
regnum 0-15 for R[0]-R[15],
16 for xPSR,
17 for Main SP,
18 for Process SP,
20 for packed control
Returns:
value

References AUTO_INCR_OFF_AP_CONTROL, CORE_DEBUG_BASE_ADDR, DHCSR_S_REGRDY, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cortex_ApAHB_BankedDataRegWrite(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_core_PollDbgState().

uint32_t jtag_cortex_core_PollDbgState ( void   ) 

Poll debug state

Return values:
0 CPU is running
1 CPU is in debug state

References AUTO_INCR_OFF_AP_CONTROL, CORE_DEBUG_BASE_ADDR, DBG_LEVEL_JTAG_ICERT_LOW, dbgPrintf(), DFSR_VCATCH, DHCSR_C_DEBUGEN, DHCSR_C_HALT, DHCSR_C_MASKINTS, DHCSR_C_SNAPSTALL, DHCSR_C_STEP, DHCSR_S_HALT, DHCSR_S_RESET_ST, DHCSR_S_RETIRE_ST, error_exit_code, ICESTATE_DCC_BUFFER_SIZE, jtag_cortex_AHB_ReadByte(), jtag_cortex_AHB_setmodeTar(), jtag_cortex_AHB_WriteByte(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cortex_ApAHB_BankedDataRegWrite(), jtag_cortex_core_Buff2Queue(), jtag_cortex_core_DebugFaultStatus_ReadRegister(), jtag_cortex_core_GetBuff(), jtag_cortex_core_ReadDebugReg(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_arm_PollDbgState(), jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_restart(), jtag_cortex_core_WriteCpuRegs(), and jtag_test().

void jtag_cortex_core_StopRunningProgram ( void   ) 

Send a manual debug request to stop the running program.

Parameters:
- 
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, CORE_DEBUG_BASE_ADDR, DBG_LEVEL_JTAG_ICERT_LOW, dbgPrintf(), DHCSR_C_DEBUGEN, DHCSR_C_HALT, DHCSR_C_MASKINTS, DHCSR_C_SNAPSTALL, DHCSR_C_STEP, DHCSR_S_HALT, DHCSR_S_RESET_ST, DHCSR_S_SLEEP, error_exit_code, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cortex_ApAHB_BankedDataRegWrite(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), SIZE_WORD_AHB_AP_CONTROL, transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by gdb_check_memory_block(), jtag_cortex_PrepareEnterDebugHalt(), stm32f10xOptionByteflashEraseSector(), and stm32FlashProgram().

void jtag_cortex_PrepareEnterDebugHalt ( void   ) 

Change internal flags of gdbserver:
set C_MASKINTS
set C_HALT
clear C_STEP
(If the Debug-Halte-State is already entered, it dose not change the Cortex Core state)

Parameters:
- 
Returns:
-

References DHCSR_C_HALT, DHCSR_C_MASKINTS, DHCSR_C_STEP, DHCSR_S_HALT, and jtag_cortex_core_StopRunningProgram().

Referenced by jtag_arm_PrepareEnterDebug().

void jtag_cortex_PrepareLeaveDebugHalt ( void   ) 

Change internal flags of gdbserver:
set C_MASKINTS
clear C_HALT
clear C_STEP
(it dose not change the Cortex Core state)

Parameters:
- 
Returns:
-

References DBG_LEVEL_GDB_ARM_ERROR, dbgPrintf(), DHCSR_C_HALT, DHCSR_C_MASKINTS, DHCSR_C_STEP, and DHCSR_S_HALT.

Referenced by jtag_cortex_core_PrepareExitDebug(), and jtag_cortex_core_RunProgram().

void jtag_cortex_core_disable_Intr ( void   ) 

Change internal flags of gdbserver:
set C_MASKINTS
(it dose not change the Cortex Core state)

Parameters:
- 
Returns:
-

References DBG_LEVEL_GDB_ARM_ERROR, dbgPrintf(), DHCSR_C_MASKINTS, and DHCSR_S_HALT.

Referenced by gdb_action_step().

void jtag_cortex_core_enable_Intr ( void   ) 

Change internal flags of gdbserver:
clear C_MASKINTS
(it dose not change the Cortex Core state)

Parameters:
- 
Returns:
-

References DBG_LEVEL_GDB_ARM_ERROR, dbgPrintf(), DHCSR_C_MASKINTS, and DHCSR_S_HALT.

Referenced by jtag_cortex_core_FinalExitDebug().

void jtag_cortex_core_PrepareExitDebug ( void   ) 

Prepare to exit debug-halt-state
Write back the stored CPU register to the ARM-Cortex-M3 core.

Parameters:
- 
Returns:
-

References jtag_cortex_core_WriteCpuRegs(), and jtag_cortex_PrepareLeaveDebugHalt().

Referenced by jtag_arm_PrepareExitDebug().

void jtag_cortex_core_FinalExitDebug ( void   ) 

Finalize: Exit debug-halt-state

Parameters:
- 
Returns:
-

References jtag_cortex_core_debugHaltingControlStatus_WriteRegister(), and jtag_cortex_core_enable_Intr().

Referenced by jtag_arm_FinalExitDebug().

void jtag_cortex_core_Step ( int  writeCpuRegs  ) 

Single step

Parameters:
writeCpuRegs 1=true; 0=false
Returns:
-

References DHCSR_C_HALT, DHCSR_C_STEP, jtag_cortex_core_debugHaltingControlStatus_WriteRegister(), and jtag_cortex_core_WriteCpuRegs().

Referenced by jtag_arm_Step(), jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_WriteCpuRegs(), and jtag_test().

void jtag_cortex_core_RunProgram ( uint32_t  address  ) 

Start execution of a program at a given address.
(start running with interrupts disabled)

Parameters:
address target machine address
Returns:
-

References CPU, jtag_cortex_core_debugHaltingControlStatus_WriteRegister(), jtag_cortex_core_WriteCpuRegs(), jtag_cortex_PrepareLeaveDebugHalt(), jtag_eos(), reg_set::Regs::r, reg_set::regs, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_arm_RunProgram().

void jtag_cortex_core_restart ( void   ) 

Try to Start (or Restart) the ARM-Cortex-M3 core

Parameters:
- 
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, reg_set::RegExt::RegV7mExt::cfsr, CPU, DBG_LEVEL_GDB_ARM_INFO, dbgPrintf(), DHCSR_C_DEBUGEN, DHCSR_C_HALT, DHCSR_C_MASKINTS, DHCSR_C_SNAPSTALL, DHCSR_C_STEP, DHCSR_S_RESET_ST, reg_set::ext, jtag_cortex_AHB_attach(), jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cortex_ApAHB_DataRegWrite(), jtag_cortex_core_ApplicationInterruptResetControl_ReadRegister(), jtag_cortex_core_ApplicationInterruptResetControl_WriteRegister(), jtag_cortex_core_ConfigurationControl_ReadRegister(), jtag_cortex_core_CPUID_ReadRegister(), jtag_cortex_core_debugExceptionMonitorControl_ReadRegister(), jtag_cortex_core_debugExceptionMonitorControl_WriteRegister(), jtag_cortex_core_DebugFaultStatus_ReadRegister(), jtag_cortex_core_debugHaltingControlStatus_ReadRegister(), jtag_cortex_core_debugHaltingControlStatus_WriteRegister(), jtag_cortex_core_HardFaultStatus_ReadRegister(), jtag_cortex_core_HardFaultStatus_WriteRegister(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_ReadCpuRegs(), jtag_cotrex_DpRdBuff_RegRead(), jtag_cotrex_DpSelect_Invalidate(), jtag_eos(), NVIC_CFSR_ADDR, SIZE_WORD_AHB_AP_CONTROL, and reg_set::RegExt::v7m.

Referenced by gdb_restart().

This file is part of the documentation for JTAG-GDB Server for ARM .
Generated on Mon Feb 15 21:23:21 2010 by doxygen 1.6.2.