jt_arm.h File Reference

Data Structures

Defines

Enumerations

Detailed Description

ARM7TDMI, ARM9TDMI and CortexM3 Definitions

Define Documentation

#define THUMB_EXPAND ( _X_   )     (((uint32_t)(_X_)<<16) | ((uint32_t)(_X_)))
#define THUMB_ADD_R0_PC   THUMB_EXPAND(0x4478)
#define THUMB_MOV_R0_PC   THUMB_EXPAND(0x4678)

Referenced by jtag_arm7_ReadCpuRegs(), and jtag_arm9_ReadCpuRegs().

#define THUMB_MOV_R8_R8   THUMB_EXPAND(0x46C0)
#define THUMB_NOP   THUMB_EXPAND(0x46C0)

Referenced by jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadCpuRegs(), jtag_arm7_Step(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadCpuRegs(), and jtag_arm9_Step().

#define THUMB_STR ( Rn,
Rd   )     THUMB_EXPAND((0x6000uL|(((uint32_t)(Rn)&7)<<3)|((uint32_t)(Rd)&7)))

Referenced by jtag_arm7_ReadCpuRegs(), and jtag_arm9_ReadCpuRegs().

#define THUMB_BX_PC   THUMB_EXPAND(0x4778)

Referenced by jtag_arm7_ReadCpuRegs(), and jtag_arm9_ReadCpuRegs().

#define THUMB_LD_R0_R2   THUMB_EXPAND(0x6810)
#define THUMB_LD_R0_R1   THUMB_EXPAND(0x6808)
#define THUMB_LD_R0_R0   THUMB_EXPAND(0x6800)
#define THUMB_LD_R0_R7   THUMB_EXPAND(0x6838)
#define THUMB_LD_R0_PC   THUMB_EXPAND(0x4800)

Referenced by jtag_arm7_PrepareExitDebug(), jtag_arm7_Step(), jtag_arm9_PrepareExitDebug(), and jtag_arm9_Step().

#define THUMB_B_dot   THUMB_EXPAND(0xe7fe)

Referenced by jtag_test().

#define THUMB_BEQ_128   THUMB_EXPAND(0xd020)
#define THUMB_BNE_128   THUMB_EXPAND(0xd120)
#define THUMB_BCS_128   THUMB_EXPAND(0xd220)
#define THUMB_BMI_128   THUMB_EXPAND(0xd420)
#define THUMB_ADC ( Rm,
Rd   )     THUMB_EXPAND((0x4140uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_ADD_IMMED_3 ( imm,
Rn,
Rd   )     THUMB_EXPAND((0x1c00uL|(((uint32_t)(imm)&7)<<6)|(((uint32_t)(Rn)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_ADD_IMMED_8 ( imm,
Rd   )     THUMB_EXPAND((0x3000uL|(((uint32_t)(Rd)&7)<<8)|((uint32_t)(imm)&0xFF)))
#define THUMB_ADD ( Rm,
Rn,
Rd   )     THUMB_EXPAND((0x1800uL|(((uint32_t)(Rm)&7)<<6)|(((uint32_t)(Rn)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_ADD_HI ( Rm,
Rd   ) 
#define THUMB_ADD_PC_IMMED_8 ( imm,
Rd   )     THUMB_EXPAND((0xa000uL|(((uint32_t)(Rd)&7)<<8)|((uint32_t)(imm)&0xFF)))
#define THUMB_ADD_SP_IMMED_8 ( imm,
Rd   )     THUMB_EXPAND((0xa800uL|(((uint32_t)(Rd)&7)<<8)|((uint32_t)(imm)&0xFF)))
#define THUMB_ADD_IMMED_7_TO_SP ( imm   )     THUMB_EXPAND((0xb000uL|((uint32_t)(imm)&0x7F)))
#define THUMB_AND ( Rm,
Rd   )     THUMB_EXPAND((0x4000uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_ASR_IMMED_5 ( imm,
Rm,
Rd   )     THUMB_EXPAND((0x1000uL|(((uint32_t)(imm)&0x1F)<<6)|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_ASR ( Rs,
Rd   )     THUMB_EXPAND((0x4100uL|(((uint32_t)(Rs)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_BIC ( Rm,
Rd   )     THUMB_EXPAND((0x4380uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_CMN ( Rm,
Rn   )     THUMB_EXPAND((0x42c0uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rn)&7)))
#define THUMB_CMP_IMMED_8 ( imm,
Rn   )     THUMB_EXPAND((0x2800uL|(((uint32_t)(Rn)&7)<<8)|((uint32_t)(imm)&0xFF)))
#define THUMB_CMP ( Rm,
Rn   )     THUMB_EXPAND((0x4280uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rn)&7)))
#define THUMB_XOR ( Rm,
Rd   )     THUMB_EXPAND((0x4040uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_LDR_IMMED_5 ( imm,
Rm,
Rd   )     THUMB_EXPAND((0x6800uL|(((uint32_t)(imm)&0x1F)<<6)|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_LDR ( Rm,
Rn,
Rd   )     THUMB_EXPAND((0x5800uL|(((uint32_t)(Rm)&7)<<6)|(((uint32_t)(Rn)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_LDR_PC ( imm,
Rd   )     THUMB_EXPAND((0x4800uL|(((uint32_t)(Rd)&7)<<8)|((uint32_t)(imm)&0xFF)))
#define THUMB_LDR_SP ( imm,
Rd   )     THUMB_EXPAND((0x9800uL|(((uint32_t)(Rd)&7)<<8)|((uint32_t)(imm)&0xFF)))
#define THUMB_LSL_IMMED_5 ( imm,
Rm,
Rd   )     THUMB_EXPAND((0x0000uL|(((uint32_t)(imm)&0x1F)<<6)|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_LSL ( Rs,
Rd   )     THUMB_EXPAND((0x4080uL|(((uint32_t)(Rs)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_LSR_IMMED_5 ( imm,
Rm,
Rd   )     THUMB_EXPAND((0x0800uL|(((uint32_t)(imm)&0x1F)<<6)|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_LSR ( Rs,
Rd   )     THUMB_EXPAND((0x40c0uL|(((uint32_t)(Rs)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_MOV_IMMED_8 ( imm,
Rd   )     THUMB_EXPAND((0x2000uL|(((uint32_t)(Rd)&7)<<8)|((uint32_t)(imm)&0xFF)))
#define THUMB_MOV ( Rn,
Rd   )     THUMB_EXPAND((0x1c00uL|(((uint32_t)(Rn)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_MUL ( Rm,
Rd   )     THUMB_EXPAND((0x4340uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_MVN ( Rm,
Rd   )     THUMB_EXPAND((0x43c0uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_NEG ( Rm,
Rd   )     THUMB_EXPAND((0x4240uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_OR ( Rm,
Rd   )     THUMB_EXPAND((0x4300uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_ROR ( Rs,
Rd   )     THUMB_EXPAND((0x41c0uL|(((uint32_t)(Rs)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_SBC ( Rm,
Rd   )     THUMB_EXPAND((0x4180uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_SUB_IMMED_3 ( imm,
Rn,
Rd   )     THUMB_EXPAND((0x1e00uL|(((uint32_t)(imm)&7)<<6)|(((uint32_t)(Rn)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_SUB_IMMED_8 ( imm,
Rd   )     THUMB_EXPAND((0x3800uL|(((uint32_t)(Rd)&7)<<8)|((uint32_t)(imm)&0xFF)))
#define THUMB_SUB ( Rm,
Rn,
Rd   )     THUMB_EXPAND((0x1a00uL|(((uint32_t)(Rm)&7)<<6)|(((uint32_t)(Rn)&7)<<3)|((uint32_t)(Rd)&7)))
#define THUMB_SUB_IMMED_7_FROM_SP ( imm   )     THUMB_EXPAND((0xb080uL|((uint32_t)(imm)&0x7F)))
#define THUMB_TST ( Rm,
Rn   )     THUMB_EXPAND((0x4200uL|(((uint32_t)(Rm)&7)<<3)|((uint32_t)(Rn)&7)))
#define ARM_NOP   0xe1a00000

Referenced by jt_amdflashProgByte_faster(), jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadByte(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ReadHalfword(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm7_Step(), jtag_arm7_WriteByte(), jtag_arm7_WriteCpuRegs(), jtag_arm7_WriteHalfword(), jtag_arm7_WriteMemoryBuf(), jtag_arm7_WriteWord(), jtag_arm920_CP15_CleanDcache(), jtag_arm920_CP15_DrainWriteBuffer(), jtag_arm920_CP15_InvalidateICache(), jtag_arm920_CP15_InvalidateTLB(), jtag_arm920_CP15_ReadDTTB(), jtag_arm920_CP15_ReadITTB(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadByte(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ReadHalfword(), jtag_arm9_ReadWord(), jtag_arm9_ReadWordMemory(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), jtag_arm9_Step(), jtag_arm9_WriteByte(), jtag_arm9_WriteCpuRegs(), jtag_arm9_WriteHalfword(), jtag_arm9_WriteMemoryBuf(), and jtag_arm9_WriteWord().

#define ARM_B_dot   0xeafffffe

Referenced by jtag_arm7_ResynchStep(), jtag_arm9_ResynchStep(), and jtag_test().

#define ARM_BX_R0   0xe12fff10

Referenced by gdb_check_thumb_support(), jtag_arm7_PrepareExitDebug(), jtag_arm7_Step(), jtag_arm9_PrepareExitDebug(), and jtag_arm9_Step().

#define ARM_LD_R0_PC   0xe59f0000

Referenced by jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadByte(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ReadHalfword(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm7_Step(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadByte(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ReadHalfword(), jtag_arm9_ReadWord(), jtag_arm9_ReadWordMemory(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_arm9_Step().

#define ARM_LD_R1_PC   0xe59f1000
#define ARM_LD_R0_R0   0xe5900000
#define ARM_LD_R1_R0   0xe5901000
#define ARM_LD_LR_R0   0xe590E000
#define ARM_STRB ( Rn,
Rd   )     (0xe5c00000|((uint32_t)(Rn)<<16)|((uint32_t)(Rd)<<12))

Referenced by jt_amdflashProgByte_faster(), jtag_arm7_WriteByte(), and jtag_arm9_WriteByte().

#define ARM_LDRB ( Rn,
Rd   )     (0xe5d00000|((uint32_t)(Rn)<<16)|((uint32_t)(Rd)<<12))

Referenced by jt_amdflashProgByte_faster(), jtag_arm7_ReadByte(), and jtag_arm9_ReadByte().

#define ARM_STRH ( Rn,
Rd   )     (0xe1c000b0|((uint32_t)(Rn)<<16)|((uint32_t)(Rd)<<12))

Referenced by jt_amdflashProgHalfword_faster(), jtag_arm7_WriteHalfword(), and jtag_arm9_WriteHalfword().

#define ARM_LDRH ( Rn,
Rd   )     (0xe1d000b0|((uint32_t)(Rn)<<16)|((uint32_t)(Rd)<<12))

Referenced by jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm7_ReadHalfword(), and jtag_arm9_ReadHalfword().

#define ARM_STR ( Rn,
Rd   )     (0xe5800000|((uint32_t)(Rn)<<16)|((uint32_t)(Rd)<<12))

Referenced by jt_amdflashProgWord_faster(), jtag_arm7_ReadCpuRegs(), jtag_arm920_CP15_CleanDcache(), jtag_arm920_CP15_DrainWriteBuffer(), jtag_arm920_CP15_InvalidateICache(), jtag_arm920_CP15_InvalidateTLB(), jtag_arm920_CP15_ReadDTTB(), jtag_arm920_CP15_ReadITTB(), and jtag_arm9_ReadCpuRegs().

#define ARM_LDR ( Rn,
Rd   )     (0xe5900000|((uint32_t)(Rn)<<16)|((uint32_t)(Rd)<<12))

Referenced by jtag_arm920_CP15_ReadDTTB(), and jtag_arm920_CP15_ReadITTB().

#define ARM_STMDB ( Rn,
Rl   )     (0xe9000000|((uint32_t)(Rn)<<16)|(Rl))
#define ARM_STMDA ( Rn,
Rl   )     (0xe8000000|((uint32_t)(Rn)<<16)|(Rl))

Referenced by jtag_arm7_ReadByte(), jtag_arm7_WriteWord(), jtag_arm9_ReadByte(), and jtag_arm9_WriteWord().

#define ARM_STMDA_S ( Rn,
Rl   )     (0xe8400000|((uint32_t)(Rn)<<16)|(Rl))
#define ARM_STMDA_BANK ( Rn,
Rl   )     (0xe8400000|((uint32_t)(Rn)<<16)|(Rl))
#define ARM_STMIA ( Rn,
Rl   )     (0xe8800000|((uint32_t)(Rn)<<16)|(Rl))

Referenced by jt_amdflashProgByte_faster(), jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ReadHalfword(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm7_WriteMemoryBuf(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ReadHalfword(), jtag_arm9_ReadWord(), jtag_arm9_ReadWordMemory(), and jtag_arm9_WriteMemoryBuf().

#define ARM_STMIA_BANK ( Rn,
Rl   )     (0xe8c00000|((uint32_t)(Rn)<<16)|(Rl))

Referenced by jtag_arm7_ReadCpuRegs(), and jtag_arm9_ReadCpuRegs().

#define ARM_LDMIA ( Rn,
Rl   )     (0xe8900000|((uint32_t)(Rn)<<16)|(Rl))

Referenced by jt_amdflashProgByte_faster(), jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm7_ResynchStep(), jtag_arm7_Step(), jtag_arm7_WriteByte(), jtag_arm7_WriteCpuRegs(), jtag_arm7_WriteHalfword(), jtag_arm7_WriteMemoryBuf(), jtag_arm7_WriteWord(), jtag_arm920_CP15_CleanDcache(), jtag_arm920_CP15_DrainWriteBuffer(), jtag_arm920_CP15_InvalidateICache(), jtag_arm920_CP15_InvalidateTLB(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadWord(), jtag_arm9_ReadWordMemory(), jtag_arm9_ResynchStep(), jtag_arm9_Step(), jtag_arm9_WriteByte(), jtag_arm9_WriteCpuRegs(), jtag_arm9_WriteHalfword(), jtag_arm9_WriteMemoryBuf(), and jtag_arm9_WriteWord().

#define ARM_LDMIA_UPDATE ( Rn,
Rl   )     (0xe8b00000|((uint32_t)(Rn)<<16)|(Rl))

Referenced by jtag_arm7_ReadWordMemory(), and jtag_arm9_ReadWordMemory().

#define ARM_LD_C ( R,
C   )     (0xe3a00000|((uint32_t)(R)<<12)|(C))
#define ARM_MOV ( Rd,
Rs   )     (0xe1a00000|((uint32_t)(Rd)<<12)|(uint32_t)(Rs))

Referenced by jtag_arm7_ReadCpuRegs(), jtag_arm7_RunProgram(), jtag_arm9_ReadCpuRegs(), and jtag_arm9_RunProgram().

#define ARM_MRS_R0_CPSR   0xe10f0000

Referenced by jtag_arm7_ReadCpuRegs(), and jtag_arm9_ReadCpuRegs().

#define ARM_MRS_R0_SPSR   0xe14f0000

Referenced by jtag_arm7_ReadCpuRegs(), and jtag_arm9_ReadCpuRegs().

#define ARM_MSR_CPSR_R0   0xe129f000

Referenced by jtag_arm7_PrepareExitDebug(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm7_Step(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_arm9_Step().

#define ARM_ADC_IMMED_8 ( rn,
rd,
imm   )     (0xe2a00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_ADC ( rn,
rd,
rm   )     (0xe0a00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_ADCS_IMMED_8 ( rn,
rd,
imm   )     (0xe2b00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_ADCS ( rn,
rd,
rm   )     (0xe0b00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_ADD_IMMED_8 ( rn,
rd,
imm   )     (0xe2800000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_ADD ( rn,
rd,
rm   )     (0xe0800000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_ADDS_IMMED_8 ( rn,
rd,
imm   )     (0xe2900000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_ADDS ( rn,
rd,
rm   )     (0xe0900000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_AND_IMMED_8 ( rn,
rd,
imm   )     (0xe2000000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_AND ( rn,
rd,
rm   )     (0xe0000000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_ANDS_IMMED_8 ( rn,
rd,
imm   )     (0xe2100000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_ANDS ( rn,
rd,
rm   )     (0xe0100000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_BIC_IMMED_8 ( rn,
rd,
imm   )     (0xe3c00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_BIC ( rn,
rd,
rm   )     (0xe1c00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_BICS_IMMED_8 ( rn,
rd,
imm   )     (0xe3d00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_BICS ( rn,
rd,
rm   )     (0xe1d00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_CMN_IMMED_8 ( rn,
imm   )     (0xe3700000|((uint32_t)(rn)<<16)|((uint32_t)(imm)&0xFF))
#define ARM_CMN ( rn,
rm   )     (0xe1700000|((uint32_t)(rn)<<16)|((uint32_t)(rm)))
#define ARM_CMP_IMMED_8 ( rn,
imm   )     (0xe3500000|((uint32_t)(rn)<<16)|((uint32_t)(imm)&0xFF))
#define ARM_CMP ( rn,
rm   )     (0xe1500000|((uint32_t)(rn)<<16)|((uint32_t)(rm)))
#define ARM_XOR_IMMED_8 ( rn,
rd,
imm   )     (0xe2200000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_XOR ( rn,
rd,
rm   )     (0xe0200000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_XORS_IMMED_8 ( rn,
rd,
imm   )     (0xe2300000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_XORS ( rn,
rd,
rm   )     (0xe0300000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_LDR_IMMED_12 ( rn,
rd,
imm   )     (0xe5900000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0x7FF))
#define ARM_MLA ( rd,
rn,
rs,
rm   )     (0xe0200090|((uint32_t)(rd)<<16)|((uint32_t)(rn)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_MLAS ( rd,
rn,
rs,
rm   )     (0xe0300090|((uint32_t)(rd)<<16)|((uint32_t)(rn)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_MOV_IMMED_8 ( rd,
imm   )     (0xe3a00000|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_MOVS_IMMED_8 ( rd,
imm   )     (0xe3b00000|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_MOVS ( rd,
rm   )     (0xe1b00000|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_MUL ( rd,
rs,
rm   )     (0xe0000090|((uint32_t)(rd)<<16)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_MULS ( rd,
rs,
rm   )     (0xe0100090|((uint32_t)(rd)<<16)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_MVN_IMMED_8 ( rd,
imm   )     (0xe3e00000|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_MVN ( rd,
rm   )     (0xe1e00000|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_MVNS_IMMED_8 ( rd,
imm   )     (0xe3f00000|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_MVNS ( rd,
rm   )     (0xe1f00000|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_ORR_IMMED_8 ( rn,
rd,
imm   )     (0xe3800000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_ORR ( rn,
rd,
rm   )     (0xe1800000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_ORRS_IMMED_8 ( rn,
rd,
imm   )     (0xe3900000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_ORRS ( rn,
rd,
rm   )     (0xe1900000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_RSB_IMMED_8 ( rn,
rd,
imm   )     (0xe2600000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_RSB ( rn,
rd,
rm   )     (0xe0600000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_RSBS_IMMED_8 ( rn,
rd,
imm   )     (0xe2700000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_RSBS ( rn,
rd,
rm   )     (0xe0700000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_RSC_IMMED_8 ( rn,
rd,
imm   )     (0xe2e00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_RSC ( rn,
rd,
rm   )     (0xe0e00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_RSCS_IMMED_8 ( rn,
rd,
imm   )     (0xe2f00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_RSCS ( rn,
rd,
rm   )     (0xe0f00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_SBC_IMMED_8 ( rn,
rd,
imm   )     (0xe2c00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_SBC ( rn,
rd,
rm   )     (0xe0c00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_SBCS_IMMED_8 ( rn,
rd,
imm   )     (0xe2d00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_SBCS ( rn,
rd,
rm   )     (0xe0d00000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_SMLAL ( rdHi,
rdLo,
rs,
rm   )     (0xe0e00090|((uint32_t)(rdHi)<<16)|((uint32_t)(rdLo)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_SMLALS ( rdHi,
rdLo,
rs,
rm   )     (0xe0f00090|((uint32_t)(rdHi)<<16)|((uint32_t)(rdLo)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_SMULL ( rdHi,
rdLo,
rs,
rm   )     (0xe0c00090|((uint32_t)(rdHi)<<16)|((uint32_t)(rdLo)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_SMULLS ( rdHi,
rdLo,
rs,
rm   )     (0xe0d00090|((uint32_t)(rdHi)<<16)|((uint32_t)(rdLo)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_STR_IMMED_12 ( rn,
rd,
imm   )     (0xe5800000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0x7FF))
#define ARM_SUB_IMMED_8 ( rn,
rd,
imm   )     (0xe2400000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_SUB ( rn,
rd,
rm   )     (0xe0400000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_SUBS_IMMED_8 ( rn,
rd,
imm   )     (0xe2500000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(imm)&0xFF))
#define ARM_SUBS ( rn,
rd,
rm   )     (0xe0500000|((uint32_t)(rn)<<16)|((uint32_t)(rd)<<12)|((uint32_t)(rm)))
#define ARM_TEQ_IMMED_8 ( rn,
imm   )     (0xe3300000|((uint32_t)(rn)<<16)|((uint32_t)(imm)&0xFF))
#define ARM_TEQ ( rn,
rm   )     (0xe1300000|((uint32_t)(rn)<<16)|((uint32_t)(rm)))
#define ARM_TST_IMMED_8 ( rn,
imm   )     (0xe3100000|((uint32_t)(rn)<<16)|((uint32_t)(imm)&0xFF))
#define ARM_TST ( rn,
rm   )     (0xe1100000|((uint32_t)(rn)<<16)|((uint32_t)(rm)))
#define ARM_UMLAL ( rdHi,
rdLo,
rs,
rm   )     (0xe0a00090|((uint32_t)(rdHi)<<16)|((uint32_t)(rdLo)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_UMLALS ( rdHi,
rdLo,
rs,
rm   )     (0xe0b00090|((uint32_t)(rdHi)<<16)|((uint32_t)(rdLo)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_UMULL ( rdHi,
rdLo,
rs,
rm   )     (0xe0800090|((uint32_t)(rdHi)<<16)|((uint32_t)(rdLo)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_UMULLS ( rdHi,
rdLo,
rs,
rm   )     (0xe0900090|((uint32_t)(rdHi)<<16)|((uint32_t)(rdLo)<<12)|((uint32_t)(rs)<<8)|((uint32_t)(rm)))
#define ARM_MRC_CP15_R1_C0_IDREG   0xee101f10
#define ARM_MRC_CP15_R2_C0_CACHEREG   0xee102f30
#define ARM_MRC_CP15_R3_C0_CNTRREG   0xee103f11
#define ARM_STORE_MSK   0x0c100000

Referenced by is_arm_store_instr().

#define ARM_STORE   0x04000000

Referenced by is_arm_store_instr().

#define ARM_STORE_MISC_MSK   0x0e100090

Referenced by is_arm_store_instr().

#define ARM_STORE_MISC   0x00000090

Referenced by is_arm_store_instr().

#define ARM_STORE_MULTIPLE_MSK   0x0e100000

Referenced by is_arm_store_instr().

#define ARM_STORE_MULTIPLE   0x08000000

Referenced by is_arm_store_instr().

#define ARM_STORE_COPROCESSOR_REG_MSK   0x0e100000

Referenced by is_arm_store_instr().

#define ARM_STORE_COPROCESSOR_REG   0x0c000000

Referenced by is_arm_store_instr().

#define THUMB_STORE_A_MSK   0xf800

Referenced by is_thumb_store_instr().

#define THUMB_STORE_A_1   0x6000

Referenced by is_thumb_store_instr().

#define THUMB_STORE_A_3   0x9000

Referenced by is_thumb_store_instr().

#define THUMB_STORE_A_BYTE_1   0x7000

Referenced by is_thumb_store_instr().

#define THUMB_STORE_A_HALF_1   0x8000

Referenced by is_thumb_store_instr().

#define THUMB_STORE_A_MULTIPLE   0xc000

Referenced by is_thumb_store_instr().

#define THUMB_STORE_B_MSK   0xfe00

Referenced by is_thumb_store_instr().

#define THUMB_STORE_B_2   0x5000

Referenced by is_thumb_store_instr().

#define THUMB_STORE_B_BYTE_2   0x5400

Referenced by is_thumb_store_instr().

#define THUMB_STORE_B_HALF_2   0x5200

Referenced by is_thumb_store_instr().

#define THUMB_STORE_B_PUSH   0xb400

Referenced by is_thumb_store_instr().

#define ARM_LOAD_MULTIPLE_BANK_MSK   0x0e508000

Referenced by is_arm_load_banked_regs_instr().

#define ARM_LOAD_MULTIPLE_BANK   0x08500000

Referenced by is_arm_load_banked_regs_instr().

#define ARM_MSR_SPSR_MSK   0x0ff0f000

Referenced by is_arm_load_banked_regs_instr().

#define ARM_MSR_SPSR_REG   0x0160f000

Referenced by is_arm_load_banked_regs_instr().

#define ARM_MSR_SPSR_IMM   0x0360f000

Referenced by is_arm_load_banked_regs_instr().

#define ARM_BLX_1_MSK   0xfe000000

Referenced by is_arm_bl_instr().

#define ARM_BLX_1_INSTR   0xfa000000

Referenced by is_arm_bl_instr().

#define ARM_BLX_2_MSK   0x0ffffff0

Referenced by is_arm_bl_instr().

#define ARM_BLX_2_INSTR   0x012fff30

Referenced by is_arm_bl_instr().

#define ARM_BL_MSK   0x0f000000

Referenced by is_arm_bl_instr().

#define ARM_BL_INSTR   0x0b000000

Referenced by is_arm_bl_instr().

#define THUMB_BL_MSK   0xf800

Referenced by gdb_action_step(), and gdb_handle_exception().

#define THUMB_BL_OFFSET_MSK   0x07ff

Referenced by gdb_action_step().

#define THUMB_BL_FIRST_PART   0xf000

Referenced by gdb_action_step(), and gdb_handle_exception().

#define THUMB_BL_SECOND_PART   0xf800

Referenced by gdb_action_step().

#define THUMB_BLX_MSK   0xf801

Referenced by gdb_action_step().

#define THUMB_BLX_SECOND_PART   0xe801

Referenced by gdb_action_step().

#define THUMB2_MRS_P1   0xf3ef

Referenced by jtag_cortex_core_ReadCpuRegs().

#define THUMB2_MRS_P2 ( Rd,
SYSm   )     (0x8000 | ((uint16_t)(Rd)<<8) | (SYSm))

Referenced by jtag_cortex_core_ReadCpuRegs().

#define THUMB2_MSR_P1 ( Rd   )     (0xf380 | (Rd))

Referenced by jtag_cortex_core_WriteCpuRegs(), and jtag_test().

#define THUMB2_MSR_P2 ( SYSm   )     (0x8800 | (SYSm))

Referenced by jtag_cortex_core_WriteCpuRegs(), and jtag_test().

#define SYSM_APSR   0

Referenced by jtag_cortex_core_WriteCpuRegs(), and jtag_test().

#define SYSM_XPSR   3
#define SYSM_MSP   8
#define SYSM_PSP   9

Referenced by jtag_test().

#define SYSM_PRIMASK   16

Referenced by jtag_cortex_core_ReadCpuRegs().

#define SYSM_BASEPRI   17

Referenced by jtag_cortex_core_ReadCpuRegs().

#define SYSM_FAULTMASK   19

Referenced by jtag_cortex_core_ReadCpuRegs(), and jtag_test().

#define SYSM_CONTROL   20

Referenced by jtag_cortex_core_ReadCpuRegs(), and jtag_test().

#define CPU_CPSR_FLAG_NEGATIVE   0x80000000uL

Referenced by arm_update_flags(), gdb_main_loop(), gdb_monitor_Rcmd(), and jt_arm_condition_check().

#define CPU_CPSR_FLAG_ZERO   0x40000000uL

Referenced by arm_update_flags(), gdb_main_loop(), gdb_monitor_Rcmd(), and jt_arm_condition_check().

#define CPU_CPSR_FLAG_CARRY   0x20000000uL

Referenced by arm_update_flags(), gdb_main_loop(), gdb_monitor_Rcmd(), and jt_arm_condition_check().

#define CPU_CPSR_FLAG_OVERFLOW   0x10000000uL

Referenced by arm_update_flags(), gdb_main_loop(), gdb_monitor_Rcmd(), and jt_arm_condition_check().

#define CPU_CPSR_FLAG_Q_STICKY_OVERFLOW   0x08000000uL

Referenced by gdb_main_loop(), and gdb_monitor_Rcmd().

#define CPU_CPSR_FLAG_IT_1   0x04000000uL
#define CPU_CPSR_FLAG_IT_0   0x02000000uL
#define CPU_CPSR_FLAG_JAZELLE   0x01000000uL

Referenced by gdb_check_thumb_support(), gdb_main_loop(), gdb_monitor_Rcmd(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ResynchStep(), and jtag_arm9_RunProgram().

#define CPU_CPSR_FLAG_FAKE_CORTEX_M3   0x00100000uL

Referenced by armOsabiGetSavedRegSet(), gdb_main_loop(), gdb_monitor_Rcmd(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_FLAG_GE_3   0x00080000uL
#define CPU_CPSR_FLAG_GE_2   0x00040000uL
#define CPU_CPSR_FLAG_GE_1   0x00020000uL
#define CPU_CPSR_FLAG_GE_0   0x00010000uL
#define CPU_CPSR_FLAG_IT_7   0x00008000uL
#define CPU_CPSR_FLAG_IT_6   0x00004000uL
#define CPU_CPSR_FLAG_IT_5   0x00002000uL
#define CPU_CPSR_FLAG_IT_4   0x00001000uL
#define CPU_CPSR_FLAG_IT_3   0x00000800uL
#define CPU_CPSR_FLAG_IT_2   0x00000400uL
#define CPU_CPSR_FLAG_ENDIAN_BIG_LDSTR   0x00000200uL
#define CPU_CPSR_FLAG_DABORT_DISABEL   0x00000100uL
#define CPU_CPSR_FLAG_IRQ_DISABEL   0x00000080uL

Referenced by armOsabiGetSavedRegSet(), gdb_action_step(), gdb_check_thumb_support(), gdb_main_loop(), gdb_monitor_Rcmd(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_FLAG_FIQ_DISABEL   0x00000040uL

Referenced by gdb_action_step(), gdb_check_thumb_support(), gdb_main_loop(), gdb_monitor_Rcmd(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_FLAG_THUMB   0x00000020uL

Referenced by armOsabiGetSavedRegSet(), gdb_action_step(), gdb_check_thumb_support(), gdb_main_loop(), gdb_monitor_Rcmd(), jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm7_Step(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), jtag_arm9_Step(), jtag_arm_Step(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_MODE_FLAGS   0x1F

Referenced by gdb_action_step(), gdb_check_thumb_support(), gdb_main_loop(), gdb_monitor_Rcmd(), is_arm_load_banked_regs_instr(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_arm9_Step().

#define CPU_CPSR_MODE_USER   0x10

Referenced by armOsabiGetSavedRegSet(), gdb_action_step(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_MODE_FIQ   0x11

Referenced by armOsabiGetSavedRegSet(), gdb_check_thumb_support(), is_arm_load_banked_regs_instr(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_MODE_IRQ   0x12

Referenced by armOsabiGetSavedRegSet(), gdb_check_thumb_support(), is_arm_load_banked_regs_instr(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_MODE_SVC   0x13

Referenced by armOsabiGetSavedRegSet(), gdb_check_thumb_support(), is_arm_load_banked_regs_instr(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_MODE_SEC_MON   0x16
#define CPU_CPSR_MODE_ABORT   0x17

Referenced by armOsabiGetSavedRegSet(), gdb_check_thumb_support(), is_arm_load_banked_regs_instr(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_MODE_UNDEF_INSTR   0x1b

Referenced by gdb_check_thumb_support(), is_arm_load_banked_regs_instr(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ResynchStep(), and jtag_arm9_RunProgram().

#define CPU_CPSR_MODE_SYSTEM   0x1F

Referenced by gdb_action_step(), gdb_check_thumb_support(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_MODE_USER_26   0x00
#define CPU_CPSR_MODE_FIQ_26   0x01
#define CPU_CPSR_MODE_IRQ_26   0x02

Referenced by armOsabiGetSavedRegSet(), and jtag_cortex_core_ReadCpuRegs().

#define CPU_CPSR_MODE_SVC_26   0x03

Referenced by armOsabiGetSavedRegSet(), and jtag_cortex_core_ReadCpuRegs().

#define DEBUG_SPEED   0

Referenced by jt_amdflashProgByte_faster(), jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadByte(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ReadHalfword(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm7_Step(), jtag_arm7_WriteByte(), jtag_arm7_WriteCpuRegs(), jtag_arm7_WriteHalfword(), jtag_arm7_WriteMemoryBuf(), jtag_arm7_WriteWord(), jtag_arm920_CP15_CleanDcache(), jtag_arm920_CP15_DrainWriteBuffer(), jtag_arm920_CP15_InvalidateICache(), jtag_arm920_CP15_InvalidateTLB(), jtag_arm920_CP15_ReadDTTB(), jtag_arm920_CP15_ReadITTB(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadByte(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ReadHalfword(), jtag_arm9_ReadWord(), jtag_arm9_ReadWordMemory(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), jtag_arm9_Step(), jtag_arm9_WriteByte(), jtag_arm9_WriteCpuRegs(), jtag_arm9_WriteHalfword(), jtag_arm9_WriteMemoryBuf(), and jtag_arm9_WriteWord().

#define SYSTEM_SPEED   1

Referenced by jt_amdflashProgByte_faster(), jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm7_mov_chain1_data(), jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadByte(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ReadHalfword(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm7_Step(), jtag_arm7_WriteByte(), jtag_arm7_WriteHalfword(), jtag_arm7_WriteMemoryBuf(), jtag_arm7_WriteWord(), jtag_arm920_CP15_CleanDcache(), jtag_arm920_CP15_DrainWriteBuffer(), jtag_arm920_CP15_InvalidateICache(), jtag_arm920_CP15_InvalidateTLB(), jtag_arm920_CP15_ReadDTTB(), jtag_arm920_CP15_ReadITTB(), jtag_arm9_mov_chain1_data(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadByte(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ReadHalfword(), jtag_arm9_ReadWord(), jtag_arm9_ReadWordMemory(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), jtag_arm9_Step(), jtag_arm9_WriteByte(), jtag_arm9_WriteHalfword(), jtag_arm9_WriteMemoryBuf(), and jtag_arm9_WriteWord().

#define DEBUG_REPEAT_SPEED   2

Referenced by jt_amdflashProgByte_faster(), jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm7_mov_chain1_data(), jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadByte(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ReadHalfword(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm7_Step(), jtag_arm7_WriteByte(), jtag_arm7_WriteCpuRegs(), jtag_arm7_WriteHalfword(), jtag_arm7_WriteMemoryBuf(), jtag_arm7_WriteWord(), jtag_arm920_CP15_CleanDcache(), jtag_arm920_CP15_DrainWriteBuffer(), jtag_arm920_CP15_InvalidateICache(), jtag_arm920_CP15_InvalidateTLB(), jtag_arm920_CP15_ReadDTTB(), jtag_arm920_CP15_ReadITTB(), jtag_arm9_mov_chain1_data(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadByte(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ReadHalfword(), jtag_arm9_ReadWord(), jtag_arm9_ReadWordMemory(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), jtag_arm9_Step(), jtag_arm9_WriteByte(), jtag_arm9_WriteCpuRegs(), jtag_arm9_WriteHalfword(), jtag_arm9_WriteMemoryBuf(), and jtag_arm9_WriteWord().

#define RESTART_SPEED   4

Referenced by jtag_arm7_mov_chain1_data(), jtag_arm7_PrepareExitDebug(), and jtag_arm9_mov_chain1_data().

#define DEBUG_NO_EOS_SPEED   8
#define DEBUG_SYSTEM_SPEED_MASK   7
#define DATA_SPEED   0x10

Referenced by jtag_arm9_mov_chain1_data().

#define WRITE_ONLY   0

Referenced by jt_amdflashProgByte_faster(), jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm720_CP15_FlushCache(), jtag_arm720_CP15_ReadFCSEpidReg(), jtag_arm720_CP15_ReadMMUcontrolReg(), jtag_arm720_CP15_ReadTTB(), jtag_arm720_CP15_WriteMMUcontrolReg(), jtag_arm720_CP15_WriteTTB(), jtag_arm720_CP15DataExchange(), jtag_arm720_CP15InstrReg(), jtag_arm7_PrepareExitDebug(), jtag_arm7_ReadByte(), jtag_arm7_ReadCP15Info(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ReadHalfword(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm7_ResynchStep(), jtag_arm7_RunProgram(), jtag_arm7_Step(), jtag_arm7_WriteByte(), jtag_arm7_WriteCpuRegs(), jtag_arm7_WriteHalfword(), jtag_arm7_WriteMemoryBuf(), jtag_arm7_WriteWord(), jtag_arm920_CP15_CleanDcache(), jtag_arm920_CP15_DrainWriteBuffer(), jtag_arm920_CP15_InvalidateICache(), jtag_arm920_CP15_InvalidateTLB(), jtag_arm920_CP15_ReadDTTB(), jtag_arm920_CP15_ReadITTB(), jtag_arm9_PrepareExitDebug(), jtag_arm9_ReadByte(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ReadHalfword(), jtag_arm9_ReadWord(), jtag_arm9_ReadWordMemory(), jtag_arm9_ResynchStep(), jtag_arm9_RunProgram(), jtag_arm9_Step(), jtag_arm9_WriteByte(), jtag_arm9_WriteCpuRegs(), jtag_arm9_WriteHalfword(), jtag_arm9_WriteMemoryBuf(), and jtag_arm9_WriteWord().

#define READ_WRITE   1

Referenced by jt_amdflashProgByte_faster(), jt_amdflashProgHalfword_faster(), jt_amdflashProgWord_faster(), jtag_arm720_CP15_ReadFCSEpidReg(), jtag_arm720_CP15_ReadMMUcontrolReg(), jtag_arm720_CP15_ReadTTB(), jtag_arm7_ReadByte(), jtag_arm7_ReadCP15Info(), jtag_arm7_ReadCpuRegs(), jtag_arm7_ReadHalfword(), jtag_arm7_ReadWord(), jtag_arm7_ReadWordMemory(), jtag_arm920_CP15_ReadDTTB(), jtag_arm920_CP15_ReadITTB(), jtag_arm9_ReadByte(), jtag_arm9_ReadCpuRegs(), jtag_arm9_ReadHalfword(), jtag_arm9_ReadWord(), and jtag_arm9_ReadWordMemory().

#define ICERT_REG_DEBUG_CONTROL   0

Referenced by jtag_arm_enterMonitorMode(), jtag_arm_FinalExitDebug(), jtag_arm_IceRT_disable_Intr(), jtag_arm_IceRT_enable_Intr(), jtag_arm_iceRT_PollDbgState(), jtag_arm_IceRT_PutAnyBreakPoint(), jtag_arm_iceRT_StopRunningProgram(), jtag_arm_Mointor2DebugMode(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_DEBUG_STATUS   1

Referenced by jtag_arm_chain1_sysspeed_restart(), jtag_arm_iceRT_PollDbgState(), jtag_arm_IceRT_PutAnyBreakPoint(), jtag_arm_IceRT_RegRead(), jtag_arm_Mointor2DebugMode(), jtag_arm_ReadCpuRegs(), jtag_arm_ResynchStep(), jtag_arm_ShowAllIceRT_Regs(), jtag_arm_Step(), and jtag_test().

#define ICERT_REG_ABORT_STATUS   2

Referenced by jtag_arm_iceRT_PollDbgState(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_VECTOR_CATCH   2

Referenced by jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_DCC_CONTROL   4

Referenced by atmelFlashClearGPNVM(), atmelFlashErase(), atmelFlashEraseAndProgram(), atmelFlashLock(), atmelFlashProgramOnly(), atmelFlashSetGPNVM(), atmelFlashUnlock(), gdb_check_memory_block(), gdb_dcc_dummy(), gdb_read_memory_block(), gdb_writeback_memory_block(), jtag_arm_iceRT_PollDbgState(), jtag_arm_IceRT_RegRead(), jtag_arm_IceRT_version(), jtag_arm_ShowAllIceRT_Regs(), philipsFlashEraseAllUnlocked(), philipsFlashLock(), philipsFlashProgram(), philipsFlashUnlock(), prog_flash_amd16(), prog_flash_amd32(), prog_flash_amd8(), str7FlashErase(), str7FlashProgram(), str9FlashErase(), and str9FlashProgram().

#define ICERT_REG_DCC_DATA   5

Referenced by atmelFlashClearGPNVM(), atmelFlashErase(), atmelFlashEraseAndProgram(), atmelFlashLock(), atmelFlashProgramOnly(), atmelFlashSetGPNVM(), atmelFlashUnlock(), gdb_check_memory_block(), gdb_dcc_dummy(), gdb_read_memory_block(), gdb_writeback_memory_block(), jtag_arm_iceRT_PollDbgState(), jtag_arm_ShowAllIceRT_Regs(), philipsFlashEraseAllUnlocked(), philipsFlashLock(), philipsFlashProgram(), philipsFlashUnlock(), prog_flash_amd16(), prog_flash_amd32(), str7FlashErase(), str7FlashProgram(), str9FlashErase(), and str9FlashProgram().

#define ICERT_REG_WATCHPOINT_0_ADDRESS   8

Referenced by jtag_arm_IceRT_PutAnyBreakPoint(), jtag_arm_IceRT_PutHWBreakPoint0(), jtag_arm_IceRT_PutWatchPoint0(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_0_ADDRMASK   9

Referenced by jtag_arm_IceRT_PutAnyBreakPoint(), jtag_arm_IceRT_PutHWBreakPoint0(), jtag_arm_IceRT_PutSWBreakPoint0(), jtag_arm_IceRT_PutWatchPoint0(), jtag_arm_Mointor2DebugMode(), jtag_arm_ShowAllIceRT_Regs(), and jtag_test().

#define ICERT_REG_WATCHPOINT_0_DATA   10

Referenced by jtag_arm_IceRT_PutSWBreakPoint0(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_0_DATAMASK   11

Referenced by jtag_arm_IceRT_PutAnyBreakPoint(), jtag_arm_IceRT_PutHWBreakPoint0(), jtag_arm_IceRT_PutSWBreakPoint0(), jtag_arm_IceRT_PutWatchPoint0(), jtag_arm_Mointor2DebugMode(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_0_CONTROL   12

Referenced by jtag_arm_IceRT_ClearAnyBreakPoint(), jtag_arm_IceRT_PutAnyBreakPoint(), jtag_arm_IceRT_PutHWBreakPoint0(), jtag_arm_IceRT_PutSWBreakPoint0(), jtag_arm_IceRT_PutWatchPoint0(), jtag_arm_Mointor2DebugMode(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_0_CONTROLMASK   13

Referenced by jtag_arm_IceRT_PutAnyBreakPoint(), jtag_arm_IceRT_PutHWBreakPoint0(), jtag_arm_IceRT_PutSWBreakPoint0(), jtag_arm_IceRT_PutWatchPoint0(), jtag_arm_Mointor2DebugMode(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_1_ADDRESS   16

Referenced by jtag_arm_IceRT_PutHWBreakPoint1(), jtag_arm_IceRT_PutWatchPoint1(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_1_ADDRMASK   17

Referenced by jtag_arm_IceRT_PutHWBreakPoint1(), jtag_arm_IceRT_PutSWBreakPoint1(), jtag_arm_IceRT_PutWatchPoint1(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_1_DATA   18

Referenced by jtag_arm_IceRT_PutSWBreakPoint1(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_1_DATAMASK   19

Referenced by jtag_arm_IceRT_PutHWBreakPoint1(), jtag_arm_IceRT_PutSWBreakPoint1(), jtag_arm_IceRT_PutWatchPoint1(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_1_CONTROL   20

Referenced by jtag_arm_IceRT_ClearAnyBreakPoint(), jtag_arm_IceRT_PutAnyBreakPoint(), jtag_arm_IceRT_PutHWBreakPoint1(), jtag_arm_IceRT_PutSWBreakPoint1(), jtag_arm_IceRT_PutWatchPoint1(), and jtag_arm_ShowAllIceRT_Regs().

#define ICERT_REG_WATCHPOINT_1_CONTROLMASK   21

Referenced by jtag_arm_IceRT_PutHWBreakPoint1(), jtag_arm_IceRT_PutSWBreakPoint1(), jtag_arm_IceRT_PutWatchPoint1(), and jtag_arm_ShowAllIceRT_Regs().

#define ICESTATE_DCC_BUFFER_SIZE   32

Referenced by jtag_cortex_core_PollDbgState().

#define ICESTATE_DCC_BUFFER_IS_EMPTY ( _TYPE_   )     (ice_state.dcc.cnt ## _TYPE_ == 0)

Referenced by gdb_handle_console_io(), and jtag_arm_iceRT_PollDbgState().

#define ICESTATE_DCC_BUFFER_IS_FULL ( _TYPE_   )     (ice_state.dcc.cnt ## _TYPE_ >= ICESTATE_DCC_BUFFER_SIZE)

Referenced by gdb_handle_console_io(), and jtag_cortex_core_Buff2Queue().

#define ICESTATE_DCC_BUFFER_INQUEUE ( _TYPE_,
_VAL_   ) 

Referenced by gdb_handle_console_io(), jtag_arm_iceRT_PollDbgState(), and jtag_cortex_core_Buff2Queue().

#define ICESTATE_DCC_BUFFER_DEQUEUE ( _TYPE_   ) 

Referenced by gdb_handle_console_io(), and jtag_arm_iceRT_PollDbgState().

#define GDB_REG_POS_THUMB_FP   7

Referenced by gdb_reply_exception().

#define GDB_REG_POS_ARM_FP   11

Referenced by gdb_reply_exception().

#define GDB_REG_POS_SP   13

Referenced by gdb_reply_exception().

#define GDB_REG_POS_LR   14

Referenced by gdb_reply_exception().

#define GDB_REG_POS_PC   15

Referenced by gdb_handle_exception(), and gdb_reply_exception().

#define GDB_REG_POS_FIRST_FLOAT   16

Referenced by gdb_handle_exception().

#define GDB_REG_POS_LAST_FLOAT   23

Referenced by gdb_handle_exception().

#define GDB_REG_POS_FLOAT_STATUS   24

Referenced by gdb_handle_exception().

#define GDB_REG_POS_PS   25

Referenced by gdb_handle_exception(), and gdb_reply_exception().

#define GDB_REG_POS_SPS   26

Referenced by gdb_handle_exception().

#define GDB_REG_POS_SLR   33

Referenced by gdb_handle_exception().

#define GDB_REG_POS_SSP   32

Referenced by gdb_handle_exception().

#define GDB_REG_POS_SR12   31

Referenced by gdb_handle_exception().

#define GDB_REG_POS_SR11   30

Referenced by gdb_handle_exception().

#define GDB_REG_POS_SR10   29

Referenced by gdb_handle_exception().

#define GDB_REG_POS_SR9   28

Referenced by gdb_handle_exception().

#define GDB_REG_POS_SR8   27

Referenced by gdb_handle_exception().

#define GDB_REG_POS_MMAR   34

Referenced by gdb_handle_exception().

#define GDB_REG_POS_BFAR   35

Referenced by gdb_handle_exception().

#define TARGET_SIGNAL_0   0

Referenced by computeSignal().

#define TARGET_SIGNAL_INT   2

Referenced by computeSignal().

#define TARGET_SIGNAL_QUIT   3

Referenced by computeSignal().

#define TARGET_SIGNAL_ILL   4

Referenced by computeSignal().

#define TARGET_SIGNAL_TRAP   5

Referenced by computeSignal().

#define TARGET_SIGNAL_ABRT   6

Referenced by computeSignal().

#define TARGET_SIGNAL_EMT   7

Referenced by computeSignal().

#define TARGET_SIGNAL_FPE   8

Referenced by computeSignal().

#define TARGET_SIGNAL_KILL   9

Referenced by computeSignal().

#define TARGET_SIGNAL_BUS   10

Referenced by computeSignal().

#define TARGET_SIGNAL_SEGV   11

Referenced by computeSignal().

#define TARGET_SIGNAL_STOP   17

Referenced by computeSignal().

#define TARGET_SIGNAL_TSTP   18

Referenced by computeSignal().

Enumeration Type Documentation

enum scan_mode

scan chain -1 - no chain selected scan chain 0 (113 bits) - Macrocell Scan Test scan chain 1 ( 33 bits) - Debug scan chain 2 ( 38 bits) - Embedded ICE logic

Enumerator:
NON 
INTEST 
EXTEST 
SYSTEM 
RESTART 
DPACC 
APACC 
DAPABORT 
This file is part of the documentation for JTAG-GDB Server for ARM .
Generated on Mon Feb 15 21:23:21 2010 by doxygen 1.6.2.