jt_cortex_break.c File Reference

#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <stdio.h>
#include <sys/time.h>
#include "dbg_msg.h"
#include "jt_arm.h"
#include "jt_cortex.h"
#include "jt_instr.h"
#include "convert.h"

Data Structures

Functions

Variables

Detailed Description

System Debug interface for ARM Cortex-M3

Function Documentation

void jtag_cortex_fpb_setup_break ( void   ) 

Setup the FPB unit

Parameters:
- 
Returns:
-

References jtag_cortex_fpb_ClearAnyHWBreakPoint(), jtag_cortex_fpb_ctrl_RegRead(), jtag_cortex_fpb_ctrl_RegWrite(), and fpb::num_bp.

Referenced by gdb_restart().

uint32_t jtag_cortex_fpb_ctrl_RegRead ( void   ) 

Read Flash Patch/Breakpoint Control Register
(saving data also in fpb.max_num_code and fpb.max_num_lit) 

 [14:12]	NUM_CODE2	(read only) 0 at Cortex-M3
 [11:8]	NUM_LIT		(read only) number of literal slots field (should be 2)
 [7:4]	NUM_CODE1	(read only) number of code slots field (shloud be 6)
 [3:2]			res
 [1]		KEY		write key = 1
 [0]		ENABLE		1=enable; 0=disable
Parameters:
- 
Returns:
value

References AUTO_INCR_OFF_AP_CONTROL, FPB_CTRL_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), fpb::max_num_code, fpb::max_num_lit, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_fpb_setup_break().

void jtag_cortex_fpb_ctrl_RegWrite ( uint32_t  enable  ) 

Write Flash Patch/Breakpoint Control Register

Parameters:
enable with value=1 to enable or value=0 disable the FPB unit
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, FPB_CTRL_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_fpb_setup_break().

uint32_t jtag_cortex_fpb_comp_RegRead ( int  number  ) 

Read Flash Patch/Breakpoint Comparator Register 

 [31:30]	REPLACE		0b00 = remap to remap address. using FPB_REMAP
 				0b01 = set BKPT on lower halfword, upper is unaffected
 				0b10 = set BKPT on upper halfword, lower is unaffected
 				0b11 = set BKPT on both lower and upper halfwords
 [29]				Reserved
 [28:2]	COMP		Comparison address
 [1]				Reserved
 [0]		ENABLE		1=enable; 0=disable
Parameters:
number number of comparator register
Returns:
value

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), FPB_COMP_BASE_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), fpb::max_num_code, fpb::max_num_lit, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

void jtag_cortex_fpb_comp_RegWrite ( int  number,
uint32_t  replace,
uint32_t  comp_addr,
uint32_t  enable 
)

Write Flash Patch/Breakpoint Comparator Register

Parameters:
number number of comparator register
replace remap, or set BRPT on lower/upper/both halfwords
comp_addr comparison address
enable to enable or disable the comparator
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), FPB_COMP_BASE_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), fpb::max_num_code, fpb::max_num_lit, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_fpb_ClearAnyHWBreakPoint(), and jtag_cortex_fpb_PutHWBreakPoint().

void jtag_cortex_fpb_PutHWBreakPoint ( uint32_t  addr,
int  len 
)

Program HW Breakpoint register to break on given address.

Parameters:
addr hardware address to break on
len 2=halfword, 4=two halfwords
Returns:
-

References DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), jtag_cortex_fpb_comp_RegWrite(), fpb::max_num_code, and fpb::num_bp.

Referenced by gdbSetupJtagTarget_Breakpoint().

void jtag_cortex_fpb_ClearAnyHWBreakPoint ( void   ) 

Disable any enabled HW breakpoint

Parameters:
- 
Returns:
-

References jtag_cortex_fpb_comp_RegWrite(), fpb::max_num_code, fpb::num_bp, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_arm_ClearAnyBreakPoint(), jtag_arm_PrepareEnterDebug(), jtag_arm_RunProgram(), and jtag_cortex_fpb_setup_break().

int jtag_cortex_fpb_get_maxBreakpoints ( void   ) 

Get maximum number of FPB breakpoints

Returns:
fpb.max_num_code

References fpb::max_num_code.

Referenced by checkActionNext(), and InsertBreakpoint().

int jtag_cortex_fpb_get_numBreakpoints ( void   ) 

Get number of FPB breakpoints currently used

Returns:
fpb.num_bp

References fpb::num_bp.

void jtag_cortex_dwt_setup_watch ( void   ) 

Setup the DWT unit

Parameters:
- 
Returns:
-

References jtag_cortex_dwt_ClearAnyWatchPoint(), jtag_cortex_dwt_ctrl_RegRead(), and dwt::num_wp.

Referenced by gdb_restart().

uint32_t jtag_cortex_dwt_ctrl_RegRead ( void   ) 

Read Data Watchpoint and Trace Control Register
(saving data also in dwt.max_num_comp) 

 [31:28]	NUMCOMP		(read only) number of comparators field (should be 4)
 [22]		CYCEVTEN	enables Cycle count event (only emitted if PCSAMPLENA, bit [12], is disabled)
 [21]		FOLDEVTENA	enables Folded instruction count event
 [20]		LSUEVTENA	enables LSU count event
 [19]		SLEEPEVTENA	enables Sleep count event
 [18]		EXCEVTENA	enables Interrupt overhead event
 [17]		CPIEVTENA	enables CPI count event
 [16]		EXCTRCENA	enables Interrupt event tracing
 [12]		PCSAMPLEENA	enables PC Sampling event
 [11:10]	SYNCTAP		feeds a synchronization pulse to the ITM SYNCENA control
 				0b00 = disabled. No synch counting
 				0b01 = tap at CYCCNT bit 24
 				0b10 = tap at CYCCNT bit 26
 				0b11 = tap at CYCCNT bit 28
 [9]		CYCTAP		selects a tap on the DWT_CYCCNT register
 				CYCTAP = 0 selects CYCCNT bit [6] to tap (when bit value changes)
 				CYCTAP = 1 selects CYCCNT bit [10] to tap (when bit value changes)
 [8:5]	POSTCNT		post-scalar counter for CYCTAP
 [4:1]	POSTPRESET	reload value for POSTCNT
 [0]		CYCCNTENA	enable the CYCCNT counter
Parameters:
- 
Returns:
value

References AUTO_INCR_OFF_AP_CONTROL, DWT_CTRL_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), dwt::max_num_comp, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_dwt_setup_watch().

void jtag_cortex_dwt_ctrl_RegWrite ( uint32_t  val  ) 

Write Data Watchpoint and Trace Control Register

Parameters:
val value to write
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, DWT_CTRL_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_DataRegWrite(), SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

uint32_t jtag_cortex_dwt_comp_RegRead ( int  number  ) 

Read Data Watchpoint and Trace Compare Address Register

 [31:0]	COMP	data value to compare against the data address as given by DWT_FUNCTIONx
Parameters:
number DWT comparator number
Returns:
value

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), DWT_COMP0_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), dwt::max_num_comp, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

void jtag_cortex_dwt_comp_RegWrite ( int  number,
uint32_t  comp_addr 
)

Write Data Watchpoint and Trace Compare Address Register

Parameters:
number DWT comparator number
comp_addr value to write
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), DWT_COMP0_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegWrite(), dwt::max_num_comp, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_dwt_PutWatchPoint().

uint32_t jtag_cortex_dwt_mask_RegRead ( int  number  ) 

Read Data Watchpoint and Trace Mask Register

 [3:0]	MASK	Mask on data address when matching against COMP.
 			This is the size of the ignore mask.
 			So, ~0<<MASK forms the mask against the address to use.
 			That is, DWT matching is performed as:
 			(ADDR & (~0 << MASK)) == COMP
Parameters:
number DWT comparator number
Returns:
value

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), DWT_COMP0_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), dwt::max_num_comp, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

void jtag_cortex_dwt_mask_RegWrite ( int  number,
uint32_t  size_of_ignore_mask 
)

Write Data Watchpoint and Trace Mask Register

Parameters:
number DWT comparator number
size_of_ignore_mask value to write
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), DWT_COMP0_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegWrite(), dwt::max_num_comp, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_dwt_PutWatchPoint().

uint32_t jtag_cortex_dwt_function_RegRead ( int  number  ) 

Read Data Watchpoint and Trace Function Register

 [24]		MATCHED		(Read Only) This bit is set when the comparator matches.(bit is cleared on read)
 [19:16]	DATAVADDR1	- see doc
 [15:12]	DATAVADDR0	- see doc
 [11:10]	DATAVSIZE	Defines the size of the data in the COMP register that is to be matched:
 				00 = byte
 				01 = halfword
 				10 = word
 				11 = Unpredictable
 [9]		LNK1ENA		(Read-only)
 				0 = DATAVADDR1 not supported
 				1 = DATAVADDR1 supported
 [8]		DATAVMATCH	- see doc
 [7]		CYCMATCH	- see doc
 [5]		EMITRANGE	- see doc
 [3:0]	FUNCTION	0b0000 disabled
 				0b0101 watchpoint on read
 				0b0110 watchpoint on write
 				0b0111 watchpoint on read or write.
Parameters:
number DWT comparatoer number
Returns:
value

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), DWT_COMP0_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegRead(), jtag_cotrex_DpRdBuff_RegRead(), jtag_eos(), dwt::max_num_comp, transaction::parameter, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

void jtag_cortex_dwt_function_RegWrite ( int  number,
uint32_t  data_size,
uint32_t  function 
)

Write Data Watchpoint and Trace Function Register

Parameters:
number DWT comparator number
data_size size value to write
function function value to write
Returns:
-

References AUTO_INCR_OFF_AP_CONTROL, DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), DWT_COMP0_ADDR, jtag_cortex_AHB_setmodeTar(), jtag_cortex_ApAHB_BankedDataRegWrite(), dwt::max_num_comp, SIZE_WORD_AHB_AP_CONTROL, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_cortex_dwt_ClearAnyWatchPoint(), and jtag_cortex_dwt_PutWatchPoint().

void jtag_cortex_dwt_PutWatchPoint ( uint32_t  addr,
int  len,
int  access 
)

Program Watchpoint register to break on given address.

Parameters:
addr hardware address to watch (should be word aligned if len >=4)
len number of bytes to watch (round up to power of 2; at least =1 then 2,4,8,16,32..32768)
access Write access(=1); Read access(=2); Read/Write access (=3)
Returns:
-

References DBG_LEVEL_GDB_ARM_WARN, dbgPrintf(), jtag_cortex_dwt_comp_RegWrite(), jtag_cortex_dwt_function_RegWrite(), jtag_cortex_dwt_mask_RegWrite(), dwt::max_num_comp, dwt::num_wp, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by gdbSetupJtagTarget_Breakpoint().

void jtag_cortex_dwt_ClearAnyWatchPoint ( void   ) 

Disable any enabled watchpoint

Parameters:
- 
Returns:
-

References jtag_cortex_dwt_function_RegWrite(), dwt::max_num_comp, dwt::num_wp, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), and transaction::uplevel.

Referenced by jtag_arm_ClearAnyBreakPoint(), jtag_arm_PrepareEnterDebug(), jtag_arm_RunProgram(), and jtag_cortex_dwt_setup_watch().

int jtag_cortex_dwt_get_maxWatchpoints ( void   ) 

Get maximum number of DWT comparator watchpoints

Returns:
dwt.max_num_comp

References dwt::max_num_comp.

Referenced by InsertBreakpoint().

int jtag_cortex_dwt_get_numWatchpoints ( void   ) 

Get number of DWT watchpoints currently used

Returns:
dwt.num_wp;

References dwt::num_wp.

Variable Documentation

struct fpb fpb = {0,0,0} [static]
struct dwt dwt = {0,0} [static]
This file is part of the documentation for JTAG-GDB Server for ARM .
Generated on Mon Feb 15 21:23:21 2010 by doxygen 1.6.2.