jt_cortex.h File Reference

Defines

#define DEFAULT_AHB_AP_CONTROL 0x23000040
Master-Debug; Prot-Priveleg;Mode-normal;transf-end;Dbg-permitted;auto increment off;size-8bit.
#define AUTO_INCR_OFF_AP_CONTROL 0x00
#define AUTO_INCR_SINGLE_AP_CONTROL 0x10
#define AUTO_INCR_PACKED_AP_CONTROL 0x20
#define SIZE_BYTE_AHB_AP_CONTROL 0
#define SIZE_HALFWORD_AHB_AP_CONTROL 1
#define SIZE_WORD_AHB_AP_CONTROL 2
#define CORE_DEBUG_BASE_ADDR 0xE000edf0
#define CORE_DEBUG_DHCSR_ADDR 0xE000edf0
#define CORE_DEBUG_DCRSR_ADDR 0xE000edf4
#define CORE_DEBUG_DCRDR_ADDR 0xE000edf8
#define CORE_DEBUG_DEMCR_ADDR 0xE000edfc
#define DHCSR_C_DEBUGEN 0x1
#define DHCSR_C_HALT 0x2
#define DHCSR_C_STEP 0x4
#define DHCSR_C_MASKINTS 0x8
#define DHCSR_C_SNAPSTALL 0x20
#define DHCSR_S_REGRDY 0x10000
#define DHCSR_S_HALT 0x20000
#define DHCSR_S_SLEEP 0x40000
#define DHCSR_S_LOCKUP 0x80000
#define DHCSR_S_RETIRE_ST 0x1000000
#define DHCSR_S_RESET_ST 0x2000000
#define DEMCR_VC_CORERESET 0x1
#define DEMCR_VC_MMERR 0x10
#define DEMCR_VC_NOCPERR 0x20
#define DEMCR_VC_CHKERR 0x40
#define DEMCR_VC_STATERR 0x80
#define DEMCR_VC_BUSERR 0x100
#define DEMCR_VC_INTERR 0x200
#define DEMCR_VC_HARDERR 0x400
#define DEMCR_MON_EN 0x10000
#define DEMCR_MON_PENG 0x20000
#define DEMCR_MON_STEP 0x40000
#define DEMCR_MON_REQ 0x80000
#define DEMCR_TRCENA 0x1000000
#define NVIC_BASE_ADDR 0xE000e000
#define NVIC_CPUID_ADDR 0xE000ed00
#define NVIC_ICSR_ADDR 0xE000ed04
#define NVIC_VTOR_ADDR 0xE000ed08
#define NVIC_AIRCR_ADDR 0xE000ed0c
#define NVIC_CCR_ADDR 0xE000ed14
#define NVIC_SHCSR_ADDR 0xE000ed24
#define NVIC_CFSR_ADDR 0xE000ed28
#define NVIC_HFSR_ADDR 0xE000ed2C
#define NVIC_DFSR_ADDR 0xE000ed30
#define NVIC_MMAR_ADDR 0xE000ed34
#define NVIC_BFAR_ADDR 0xE000ed38
#define AIRCR_SYSRESETREQ 0x4
#define AIRCR_VECTRESET 0x1
#define DFSR_EXTERNAL 0x10
#define DFSR_VCATCH 0x08
#define DFSR_DWTTRAP 0x04
#define DFSR_BKPT 0x02
#define DFSR_HALTED 0x01
#define FPB_CTRL_ADDR 0xE0002000
#define FPB_REMAP_ADDR 0xE0002004
#define FPB_COMP_BASE_ADDR 0xE0002008
#define DWT_CTRL_ADDR 0xE0001000
#define DWT_CYCCNT_ADDR 0xE0001004
#define DWT_CPICNT_ADDR 0xE0001008
#define DWT_EXCCNT_ADDR 0xE000100C
#define DWT_SLEEPCNT_ADDR 0xE0001010
#define DWT_LSUCNT_ADDR 0xE0001014
#define DWT_FOLDCNT_ADDR 0xE0001018
#define DWT_PCSR_ADDR 0xE000101C
#define DWT_COMP0_ADDR 0xE0001020
#define DWT_MASK0_ADDR 0xE0001024
#define DWT_FUNCTION0_ADDR 0xE0001028
#define DWT_COMP1_ADDR 0xE0001030
#define DWT_MASK1_ADDR 0xE0001034
#define DWT_FUNCTION1_ADDR 0xE0001038
#define DWT_COMP2_ADDR 0xE0001040
#define DWT_MASK2_ADDR 0xE0001044
#define DWT_FUNCTION2_ADDR 0xE0001048
#define DWT_COMP3_ADDR 0xE0001050
#define DWT_MASK3_ADDR 0xE0001054
#define DWT_FUNCTION3_ADDR 0xE0001058

Detailed Description

ARM Cortex-M3 Definitions

Define Documentation

#define DEFAULT_AHB_AP_CONTROL 0x23000040

Master-Debug; Prot-Priveleg;Mode-normal;transf-end;Dbg-permitted;auto increment off;size-8bit.

Referenced by jtag_cortex_AHB_attach(), and jtag_cortex_AHB_setmodeTar().

#define AUTO_INCR_OFF_AP_CONTROL 0x00

#define AUTO_INCR_SINGLE_AP_CONTROL 0x10

Referenced by jtag_cortex_AHB_ReadWordMemory(), and jtag_cortex_AHB_WriteMemoryBuf().

#define AUTO_INCR_PACKED_AP_CONTROL 0x20

#define SIZE_BYTE_AHB_AP_CONTROL 0

Referenced by jtag_cortex_AHB_ReadByte().

#define SIZE_HALFWORD_AHB_AP_CONTROL 1

Referenced by jtag_cortex_AHB_ReadHalfword().

#define SIZE_WORD_AHB_AP_CONTROL 2

#define CORE_DEBUG_BASE_ADDR 0xE000edf0

Referenced by jtag_cortex_core_debugExceptionMonitorControl_ReadRegister(), jtag_cortex_core_debugExceptionMonitorControl_WriteRegister(), jtag_cortex_core_debugHaltingControlStatus_ReadRegister(), jtag_cortex_core_debugHaltingControlStatus_WriteRegister(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_ReadDebugReg(), jtag_cortex_core_StopRunningProgram(), jtag_cortex_core_WriteCpuRegs(), and jtag_test().

#define CORE_DEBUG_DHCSR_ADDR 0xE000edf0

DEBUG HALTING CONTROL AND STATUS REGISTER

#define CORE_DEBUG_DCRSR_ADDR 0xE000edf4

DEBUG CORE REGISTER SELECTOR REGISTER

#define CORE_DEBUG_DCRDR_ADDR 0xE000edf8

DEBUG CORE REGISTER DATA REGISTER

#define CORE_DEBUG_DEMCR_ADDR 0xE000edfc

DEBUG EXEPTION AND MONITOR CONTROL REGISTER

#define DHCSR_C_DEBUGEN 0x1

Referenced by jtag_cortex_core_PollDbgState(), jtag_cortex_core_restart(), jtag_cortex_core_StopRunningProgram(), and jtag_cortex_core_WriteCpuRegs().

#define DHCSR_C_HALT 0x2

Referenced by jtag_cortex_core_PollDbgState(), jtag_cortex_core_restart(), jtag_cortex_core_Step(), jtag_cortex_core_StopRunningProgram(), jtag_cortex_PrepareEnterDebugHalt(), and jtag_cortex_PrepareLeaveDebugHalt().

#define DHCSR_C_STEP 0x4

Referenced by jtag_cortex_core_PollDbgState(), jtag_cortex_core_restart(), jtag_cortex_core_Step(), jtag_cortex_core_StopRunningProgram(), jtag_cortex_PrepareEnterDebugHalt(), and jtag_cortex_PrepareLeaveDebugHalt().

#define DHCSR_C_MASKINTS 0x8

Referenced by jtag_cortex_core_disable_Intr(), jtag_cortex_core_enable_Intr(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_restart(), jtag_cortex_core_StopRunningProgram(), jtag_cortex_PrepareEnterDebugHalt(), and jtag_cortex_PrepareLeaveDebugHalt().

#define DHCSR_C_SNAPSTALL 0x20

Referenced by jtag_cortex_core_PollDbgState(), jtag_cortex_core_restart(), jtag_cortex_core_StopRunningProgram(), and jtag_test().

#define DHCSR_S_REGRDY 0x10000

Referenced by jtag_cortex_core_ReadCpuRegs(), jtag_cortex_core_ReadDebugReg(), jtag_cortex_core_WriteCpuRegs(), and jtag_test().

#define DHCSR_S_HALT 0x20000

Referenced by jtag_cortex_core_disable_Intr(), jtag_cortex_core_enable_Intr(), jtag_cortex_core_PollDbgState(), jtag_cortex_core_StopRunningProgram(), jtag_cortex_core_WriteCpuRegs(), jtag_cortex_PrepareEnterDebugHalt(), and jtag_cortex_PrepareLeaveDebugHalt().

#define DHCSR_S_SLEEP 0x40000

Referenced by jtag_cortex_core_StopRunningProgram().

#define DHCSR_S_LOCKUP 0x80000

#define DHCSR_S_RETIRE_ST 0x1000000

Referenced by jtag_cortex_core_PollDbgState().

#define DHCSR_S_RESET_ST 0x2000000

Referenced by jtag_cortex_core_PollDbgState(), jtag_cortex_core_restart(), and jtag_cortex_core_StopRunningProgram().

#define DEMCR_VC_CORERESET 0x1

#define DEMCR_VC_MMERR 0x10

#define DEMCR_VC_NOCPERR 0x20

#define DEMCR_VC_CHKERR 0x40

#define DEMCR_VC_STATERR 0x80

#define DEMCR_VC_BUSERR 0x100

#define DEMCR_VC_INTERR 0x200

#define DEMCR_VC_HARDERR 0x400

#define DEMCR_MON_EN 0x10000

#define DEMCR_MON_PENG 0x20000

#define DEMCR_MON_STEP 0x40000

#define DEMCR_MON_REQ 0x80000

#define DEMCR_TRCENA 0x1000000

#define NVIC_BASE_ADDR 0xE000e000

#define NVIC_CPUID_ADDR 0xE000ed00

CPUID Register

Referenced by jtag_cortex_core_CPUID_ReadRegister().

#define NVIC_ICSR_ADDR 0xE000ed04

Interrupt Control State Register

Referenced by jtag_cortex_core_ReadCpuRegs().

#define NVIC_VTOR_ADDR 0xE000ed08

Vector Table Offest Register

Referenced by jtag_cortex_core_ReadCpuRegs().

#define NVIC_AIRCR_ADDR 0xE000ed0c

Application Interrupt/Reset Control Register

Referenced by jtag_cortex_core_ApplicationInterruptResetControl_ReadRegister(), and jtag_cortex_core_ApplicationInterruptResetControl_WriteRegister().

#define NVIC_CCR_ADDR 0xE000ed14

Configuration Control Register

Referenced by jtag_cortex_core_ConfigurationControl_ReadRegister(), and jtag_cortex_core_ConfigurationControl_WriteRegister().

#define NVIC_SHCSR_ADDR 0xE000ed24

System Handler Control and Status Register

Referenced by jtag_cortex_core_ReadCpuRegs().

#define NVIC_CFSR_ADDR 0xE000ed28

Configurable Fault Status Register

Referenced by jtag_cortex_core_ReadCpuRegs(), and jtag_cortex_core_restart().

#define NVIC_HFSR_ADDR 0xE000ed2C

Hard Fault Status Register

Referenced by jtag_cortex_core_HardFaultStatus_ReadRegister(), and jtag_cortex_core_HardFaultStatus_WriteRegister().

#define NVIC_DFSR_ADDR 0xE000ed30

Debug Fault Status Register

Referenced by jtag_cortex_core_DebugFaultStatus_ReadRegister(), and jtag_cortex_core_DebugFaultStatus_WriteRegister().

#define NVIC_MMAR_ADDR 0xE000ed34

Mem Mangage Address Register

Referenced by jtag_cortex_core_MemManageAddress_ReadRegister(), and jtag_cortex_core_MemManageAddress_WriteRegister().

#define NVIC_BFAR_ADDR 0xE000ed38

Bus Fault Address Register

Referenced by jtag_cortex_core_BusFaultAddress_ReadRegister(), and jtag_cortex_core_BusFaultAddress_WriteRegister().

#define AIRCR_SYSRESETREQ 0x4

#define AIRCR_VECTRESET 0x1

#define DFSR_EXTERNAL 0x10

#define DFSR_VCATCH 0x08

Referenced by jtag_cortex_core_PollDbgState().

#define DFSR_DWTTRAP 0x04

#define DFSR_BKPT 0x02

#define DFSR_HALTED 0x01

#define FPB_CTRL_ADDR 0xE0002000

Flash Patch/Breakpoint Control Register

Referenced by jtag_cortex_fpb_ctrl_RegRead(), and jtag_cortex_fpb_ctrl_RegWrite().

#define FPB_REMAP_ADDR 0xE0002004

Flash Patch Remap Register

#define FPB_COMP_BASE_ADDR 0xE0002008

Base Addrss of all Flash Patch/Breakpoint Comparator Registers

Referenced by jtag_cortex_fpb_comp_RegRead(), and jtag_cortex_fpb_comp_RegWrite().

#define DWT_CTRL_ADDR 0xE0001000

Data Watchpoint and Trace Control Register

Referenced by jtag_cortex_dwt_ctrl_RegRead(), and jtag_cortex_dwt_ctrl_RegWrite().

#define DWT_CYCCNT_ADDR 0xE0001004

Data Watchpoint and Trace Current PC Sampler Cycle Count

#define DWT_CPICNT_ADDR 0xE0001008

Data Watchpoint and Trace CPI Count Register

#define DWT_EXCCNT_ADDR 0xE000100C

Data Watchpoint and Trace Exception Overhead Count Register

#define DWT_SLEEPCNT_ADDR 0xE0001010

Data Watchpoint and Trace Sleep Count Register

#define DWT_LSUCNT_ADDR 0xE0001014

Data Watchpoint and Trace LSU Count Register

#define DWT_FOLDCNT_ADDR 0xE0001018

Data Watchpoint and Trace Fold Count Register

#define DWT_PCSR_ADDR 0xE000101C

Data Watchpoint and Trace Fold Counter Sample Register

#define DWT_COMP0_ADDR 0xE0001020

Data Watchpoint and Trace Fold Comparator Registers

Referenced by jtag_cortex_dwt_comp_RegRead(), jtag_cortex_dwt_comp_RegWrite(), jtag_cortex_dwt_function_RegRead(), jtag_cortex_dwt_function_RegWrite(), jtag_cortex_dwt_mask_RegRead(), and jtag_cortex_dwt_mask_RegWrite().

#define DWT_MASK0_ADDR 0xE0001024

Data Watchpoint and Trace Mask Registers

#define DWT_FUNCTION0_ADDR 0xE0001028

Data Watchpoint and Trace Function Registers

#define DWT_COMP1_ADDR 0xE0001030

Data Watchpoint and Trace Fold Comparator Registers

#define DWT_MASK1_ADDR 0xE0001034

Data Watchpoint and Trace Mask Registers

#define DWT_FUNCTION1_ADDR 0xE0001038

Data Watchpoint and Trace Function Registers

#define DWT_COMP2_ADDR 0xE0001040

Data Watchpoint and Trace Fold Comparator Registers

#define DWT_MASK2_ADDR 0xE0001044

Data Watchpoint and Trace Mask Registers

#define DWT_FUNCTION2_ADDR 0xE0001048

Data Watchpoint and Trace Function Registers

#define DWT_COMP3_ADDR 0xE0001050

Data Watchpoint and Trace Fold Comparator Registers

#define DWT_MASK3_ADDR 0xE0001054

Data Watchpoint and Trace Mask Registers

#define DWT_FUNCTION3_ADDR 0xE0001058

Data Watchpoint and Trace Function Registers