#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <stdio.h>
#include "dbg_msg.h"
#include "arm_emu.h"
#include "jt_arm.h"
#include "jt_mmu.h"
#include "jt_instr.h"
ARM7TDMI Interface
The ARM7TDMI core uses scan chain 1 with a wide of 33 bits to send instructions and exchange data values to the debug unit.
void jtag_arm7_ReadCpuRegs | ( | int | reset_inst_counter, | |
int | status | |||
) |
Read out ARM CPU core registers R0..R15 and CPSR.
The values are stored inside of the global structure named CPU.
status | indicate if machine enter debug state from ARM or THUMB mode | |
reset_inst_counter | try to reset PC |
References ARM_LD_R0_PC, ARM_MOV, ARM_MRS_R0_CPSR, ARM_MRS_R0_SPSR, ARM_NOP, ARM_STMIA, ARM_STMIA_BANK, ARM_STR, reg_set::CPSR, CPU, CPU_CPSR_FLAG_THUMB, CPU_CPSR_MODE_ABORT, CPU_CPSR_MODE_FIQ, CPU_CPSR_MODE_FLAGS, CPU_CPSR_MODE_IRQ, CPU_CPSR_MODE_SVC, CPU_CPSR_MODE_UNDEF_INSTR, DEBUG_REPEAT_SPEED, DEBUG_SPEED, reg_set::ext, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), jtag_eos(), reg_set::RegExt::RegV4Ext::lr_usr, transaction::parameter, reg_set::RegExt::RegV4Ext::prev_CPSR, reg_set::Regs::r, reg_set::RegExt::RegV4Ext::r10_usr, reg_set::RegExt::RegV4Ext::r11_usr, reg_set::RegExt::RegV4Ext::r12_usr, reg_set::RegExt::RegV4Ext::r8_usr, reg_set::RegExt::RegV4Ext::r9_usr, READ_WRITE, reg_set::regs, reg_set::RegExt::RegV4Ext::sp_usr, reg_set::RegExt::RegV4Ext::SPSR, SYSTEM_SPEED, THUMB_BX_PC, THUMB_MOV_R0_PC, THUMB_NOP, THUMB_STR, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transaction::uplevel, reg_set::RegExt::v4, and WRITE_ONLY.
Referenced by jtag_arm_ReadCpuRegs().
void jtag_arm7_WriteCpuRegs | ( | void | ) |
Write back the stored CPU register to the ARM core.
(This function is used for test only.)
- |
References ARM_LDMIA, ARM_NOP, CPU, DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), reg_set::Regs::r, reg_set::regs, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_WriteCpuRegs().
void jtag_arm7_PrepareExitDebug | ( | void | ) |
Write back the stored CPU register to the ARM core and restart execution to continue the current program.
-- note on exit we messed up the PC so we can't access the Memory within the debug state.
But we can correct this next time we read out the CPU register
- |
References ARM_BX_R0, ARM_LD_R0_PC, ARM_LDMIA, ARM_MSR_CPSR_R0, ARM_NOP, reg_set::CPSR, CPU, CPU_CPSR_FLAG_THUMB, DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), reg_set::Regs::r, reg_set::regs, RESTART_SPEED, SYSTEM_SPEED, THUMB_LD_R0_PC, THUMB_NOP, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_PrepareExitDebug().
void jtag_arm7_Step | ( | uint32_t | next_instr | ) |
Single step (ARM7TDMI)
Write back the stored CPU register to the ARM core and execute one instruction.
The instruction has to be executed is given in next_instr.
next_instr | ARM or THUMB instruction to execute |
References ARM_BX_R0, ARM_LD_R0_PC, ARM_LDMIA, ARM_MSR_CPSR_R0, ARM_NOP, reg_set::CPSR, CPU, CPU_CPSR_FLAG_THUMB, DBG_LEVEL_GDB_ARM_INFO, dbgPrintf(), DEBUG_REPEAT_SPEED, DEBUG_SPEED, jt_arm_instr_access_mem(), jt_arm_instr_modifys_PC(), jt_thumb_instr_access_mem(), jt_thumb_instr_modifys_PC(), jtag_arm7_mov_chain1_data(), reg_set::Regs::r, reg_set::regs, SYSTEM_SPEED, THUMB_LD_R0_PC, THUMB_NOP, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_Step().
void jtag_arm7_ResynchStep | ( | void | ) |
Resynchronize step at ARM7TDMI.
Write back some of the stored CPU register to the ARM core and execute one "b ." instruction.
- |
References ARM_B_dot, ARM_LD_R0_PC, ARM_LDMIA, ARM_MSR_CPSR_R0, ARM_NOP, reg_set::CPSR, CPU, CPU_CPSR_FLAG_FIQ_DISABEL, CPU_CPSR_FLAG_IRQ_DISABEL, CPU_CPSR_FLAG_JAZELLE, CPU_CPSR_FLAG_THUMB, CPU_CPSR_MODE_ABORT, CPU_CPSR_MODE_FIQ, CPU_CPSR_MODE_FLAGS, CPU_CPSR_MODE_IRQ, CPU_CPSR_MODE_SVC, CPU_CPSR_MODE_SYSTEM, CPU_CPSR_MODE_UNDEF_INSTR, CPU_CPSR_MODE_USER, DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), reg_set::Regs::r, reg_set::regs, SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_ResynchStep().
void jtag_arm7_ReadWordMemory | ( | uint32_t | address, | |
int | howmanywords, | |||
uint32_t * | buf | |||
) |
Read out word memory into the given buffer.
Max read speed : 19 Kbytes/sec
address | target machine address (memory at ARM side) | |
howmanywords | number of words to read | |
buf | pointer to destination read buffer (memory at server side) |
References ARM_LD_R0_PC, ARM_LDMIA, ARM_LDMIA_UPDATE, ARM_NOP, ARM_STMIA, DBG_LEVEL_GDB_ARM_INFO, dbgPrintf(), DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), transaction::parameter, READ_WRITE, SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_ReadWordMemory().
uint32_t jtag_arm7_ReadWord | ( | uint32_t | address | ) |
32 Bit Word Read
CPU must be in debug state
address | target machine address (memory at ARM side) |
References ARM_LD_R0_PC, ARM_LDMIA, ARM_NOP, ARM_STMIA, DBG_LEVEL_JTAG_ARM_LOW, dbgPrintf(), DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), transaction::parameter, READ_WRITE, SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_ReadWord().
uint32_t jtag_arm7_ReadHalfword | ( | uint32_t | address | ) |
16 Bit Halfword Read
address | target machine address (memory at ARM side) |
References ARM_LD_R0_PC, ARM_LDRH, ARM_NOP, ARM_STMIA, DBG_LEVEL_JTAG_ARM_LOW, dbgPrintf(), DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), transaction::parameter, READ_WRITE, SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_ReadHalfword().
uint32_t jtag_arm7_ReadByte | ( | uint32_t | address | ) |
8 Bit Byte Read
address | target machine address (memory at ARM side) |
References ARM_LD_R0_PC, ARM_LDRB, ARM_NOP, ARM_STMDA, DBG_LEVEL_JTAG_ARM_LOW, dbgPrintf(), DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), transaction::parameter, READ_WRITE, SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_ReadByte().
void jtag_arm7_WriteWord | ( | uint32_t | address, | |
uint32_t | value | |||
) |
32-bit memory write
address | target machine address (memory at ARM side) | |
value | 32 bit value to write |
References ARM_LDMIA, ARM_NOP, ARM_STMDA, DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_WriteWord().
void jtag_arm7_WriteHalfword | ( | uint32_t | address, | |
uint16_t | value | |||
) |
16-bit memory write
address | target machine address (memory at ARM side) | |
value | 16 bit value to write |
References ARM_LDMIA, ARM_NOP, ARM_STRH, DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_WriteHalfword().
void jtag_arm7_WriteByte | ( | uint32_t | address, | |
uint16_t | value | |||
) |
8-bit memory write
address | target machine address (memory at ARM side) | |
value | 8 bit value to write |
References ARM_LDMIA, ARM_NOP, ARM_STRB, DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_WriteByte().
void jtag_arm7_WriteMemoryBuf | ( | uint32_t | address, | |
int | howmanywords, | |||
uint32_t * | buf | |||
) |
Write back word memory from the given buffer.
address | target machine address (memory at ARM side) | |
howmanywords | number of words to read | |
buf | pointer to source write buffer (memory at server side) |
References ARM_LDMIA, ARM_NOP, ARM_STMIA, DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), jtag_arm_chain1_sysspeed_restart(), SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionGet(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_WriteMemoryBuf().
void jtag_arm7_RunProgram | ( | uint32_t | address | ) |
Start execution of a program at a given address.
address | target machine address (memory at ARM side) |
References ARM_LD_R0_PC, ARM_MOV, ARM_MSR_CPSR_R0, ARM_NOP, reg_set::CPSR, CPU, CPU_CPSR_FLAG_FIQ_DISABEL, CPU_CPSR_FLAG_IRQ_DISABEL, CPU_CPSR_FLAG_JAZELLE, CPU_CPSR_FLAG_THUMB, CPU_CPSR_MODE_ABORT, CPU_CPSR_MODE_FIQ, CPU_CPSR_MODE_FLAGS, CPU_CPSR_MODE_IRQ, CPU_CPSR_MODE_SVC, CPU_CPSR_MODE_SYSTEM, CPU_CPSR_MODE_UNDEF_INSTR, CPU_CPSR_MODE_USER, DEBUG_REPEAT_SPEED, DEBUG_SPEED, jtag_arm7_mov_chain1_data(), SYSTEM_SPEED, transactionActivate(), transactionCreate(), transactionErase(), transactionExecute(), transactionGet(), transactionPenting(), transaction::uplevel, and WRITE_ONLY.
Referenced by jtag_arm_RunProgram().