MMU Definitions
| #define ARM_MRC_CP15_R0_C0_IDREG 0xee100f10 |
Referenced by jtag_arm7_ReadCP15Info().
| #define ARM_MRC_CP15_R0_C0_CACHEREG 0xee100f30 |
Referenced by jtag_arm7_ReadCP15Info().
| #define ARM_MRC_CP15_R0_C1_MMUCNTRREG 0xee110f10 |
Referenced by jtag_arm720_CP15_ReadMMUcontrolReg().
| #define ARM_MCR_CP15_R0_C1_MMUCNTRREG 0xee010f10 |
Referenced by jtag_arm720_CP15_WriteMMUcontrolReg().
| #define ARM_MRC_CP15_R0_C13_FCSE_IDREG 0xee1d0f10 |
Referenced by jtag_arm720_CP15_ReadFCSEpidReg().
| #define ARM_MRC_CP15_5_R0_C15_C1_2 0xeebf0f51 |
Referenced by jtag_arm920_CP15_ReadITTB().
| #define ARM_MRC_CP15_0_R0_C2_C2_2 0xee120f52 |
Referenced by jtag_arm920_CP15_ReadDTTB().
| #define ARM_MRC_CP15_0_R0_C2_C0_0 0xee120f10 |
Referenced by jtag_arm720_CP15_ReadTTB().
| #define ARM_MCR_CP15_0_R0_C2_C0_0 0xee020f10 |
Referenced by jtag_arm720_CP15_WriteTTB().
| #define ARM_MCR_CP15_0_R0_C7_C10_2 0xee070f5a |
Referenced by jtag_arm920_CP15_CleanDcache().
| #define ARM_MCR_CP15_0_R0_C7_C10_4 0xee070f9a |
Referenced by jtag_arm920_CP15_DrainWriteBuffer().
| #define ARM_MCR_CP15_0_R0_C7_C5_0 0xee070f15 |
Referenced by jtag_arm920_CP15_InvalidateICache().
| #define ARM_MCR_CP15_0_R0_C8_C7_0 0xee080f17 |
Referenced by jtag_arm920_CP15_InvalidateTLB().
| #define ARM_MCR_CP15_0_R0_C7_C7_0 0xee070f17 |
Referenced by jtag_arm720_CP15_FlushCache().
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_IDCODE 0x00 |
Referenced by jtag_arm9_ReadCP15Info().
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_CACHETYPE 0x01 |
Referenced by jtag_arm9_ReadCP15Info().
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_MMUCONTROL 0x02 |
Referenced by jtag_test().
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_D_CACHE_LOCKDOWN 0x12 |
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_I_CACHE_LOCKDOWN 0x13 |
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_FCSE_PID 0x1A |
Referenced by jtag_test().
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_C15_STATE 0x1E |
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_C15_ICACHE_IDX 0x3B |
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_C15_DCACHE_IDX 0x3D |
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_C15_ICACHE 0x23 |
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_C15_DCACHE 0x25 |
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_C15_IMMU 0x2A |
| #define MMU920_PHYSACCESS_CP15_REGADDRESS_C15_DMMU 0x2C |
| #define TCM966_ENABLE_ITCM (1<<12) |
Referenced by jtag_test().
| #define TCM966_BIGENDIAN (1<<7) |
| #define TCM966_ENABLE_AHB_WRITE_BUFFER (1<<3) |
Referenced by jtag_test().
| #define TCM966_ENABLE_DTCM (1<<2) |
Referenced by jtag_test().
| #define TCM966_ENABLE_ALIGNMENT_CHECK (1<<1) |