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# Command line options
#
jtag_server [OPTIONS] -driver NAME HOST:PORT
jtag_server [OPTIONS] -driver NAME -iotest
jtag_server [OPTIONS] -driver NAME -testjtag TESTLIST
NAME: name of a cable driver
tls my own TINKER LEVEL SHIFTER
tbdm an other TINKER hardware called BDM
tlongo the TINKER hardware from R.Longo
omsp modified OLIMEX MSP430
wiggler OCDEMON WIGGLER
bblst ALTERA BYTEBLASTER
ispl LATTICE ISPDLC
dlc XILINX DLC
apod AMONTEC EPP ACCELERATOR
usbjlink Segger J-Link USB JTAG driver
usbftdi_vid_pid Ftdi-Chip FT2232c based USB JTAG driver
with vid_pid = vendor id and product id e.g. a5a5_1234
usbftdi_vid_pid_variant
with variant = olimex jtagkey flyswatter turtelizer2
str9comstick stm32stick
oocdjtag signalyzer oocdlink
usbftdi_vid_pid_variant_reset
with reset = SRstPP TRstPP SRstPP_TRstPPPORT: listen at "PORT" for a TCP connection.
HOST: allow only client with "HOST" address to be connect
if no HOST address is given defaults to 127.0.0.1 (local host)
OPTIONS:
-? print command line help info
-help print gdb remote help info
-V Display the program's version number
-v send a more verbose info string to gdb
(default LESS VERBOSE)
-d# level of debug messages, where # is a number [0..9]
0 - no debug messages
1 - DBG_LEVEL_GDB_ARM_ERROR
2 - same as 1 plus DBG_LEVEL_GDB_ARM_WARN
3 - same as 2 plus DBG_LEVEL_GDB_ARM_INFO
4 - same as 3 plus DBG_LEVEL_JTAG_ARM
5 - same as 4 plus DBG_LEVEL_JTAG_ARM_LOW
6 - same as 4 plus DBG_LEVEL_GDB_ARM_INFO_LOW
7 - same as 5 plus DBG_LEVEL_JTAG_ICERT
8 - same as 6 plus DBG_LEVEL_JTAG_ICERT_LOW and DBG_LEVEL_JTAG_INSTR
9 - same as 7 plus DBG_LEVEL_JTAG_TAP
(default level is 5)
-7 ARM7TDMI Core (default)
-720 ARM720T rev 3 Core
-9 ARM9TDMI Core
-cortex ARM Cortex M3 Core
-be Big Endian (not yet supported)
-le Little Endian (default)
-lptbase 0x### port address eiher 0x3BC, 0x378, 0x278 or
at pci baseaddr. >= 0x1000 (very dangerous)
(default lptbase = 0x378)
-rstgrant # time in milliseconds -- GRANT SRESET line
-rstsettle # time in milliseconds -- CPU init time
-rstkeep keep holding the SRESET line during CPU/debug init phase (at CortexM3 using wiggler)
-tClk # tap clock frequency (in Hz)
-config FILE (experimental hack for GDB new vFlash stuff -- still not usefull)
-testrambase 0x###
-testflashbase 0x###-iotest: a raw io test to check the cable driver (NEVER connect it with a real target machine)
-testjtag: a simple JTAG-ARM test
TESTLIST: #[,#] comma seperated list e.g. 0,1
0 detect JTAG-ID
1 show ICE and CPU Regs
2 ICE modify
3 Flash info/read (requires testflashbase)
4 RAM read/write test (requires testrambase)
5 RAM program test (requires testrambase)
6 read RAM (requires testrambase)
7 Write CPU Regs
8 do 15 step intruczions from address 0x0
9 ARM emulator/function test
10 Thumb emulator/function test
11 release CPU# some ram base addresse
# 0x0c000000 @ samsung s3c44b0x (sdram)
# 0x10001000 @ samsung s3c44b0x (internal sram -- if cache disabled)
# 0x40000000 @ philips lpc2106 (internal sram)
# 0x00200000 @ atmel at91sam7 (internal sram)
# 0x00200000 @ atmel at91rm9200 (internal sram)
# 0x20000000 @ atmel at91rm9200 (sdram)
# 0x20000000 @ stm str71x (internal sram)
# 0x50000000 @ stm str91x (internal sram AHB non bufferd)
# 0x40000000 @ stm str91x (internal sram AHB bufferd)
# 0x04000000 @ stm str91x (internal sram 64K D-TCM)
# 0x20000000 @ sharp lh79520 (sdram)
# 0x60000000 @ sharp lh79520 (internal sram)
# some flash base addresses
# 0x00000000 @ samsung s3c44b0x (external)
# 0x00000000 @ philips lpc2106 (internal)
# 0x00100000 @ atmel at91sam7 (internal)
# 0x40000000 @ stm str71x (internal Flash Bank 0)
# 0x400C0000 @ stm str71x (internal Flash Bank 1)
# 0x40000000 @ sharp lh79520 (external)